Module physical 

The card’s memory as its four channels hold it: where every byte of a machine layout (super::machine::Layout) lives, and the streams a job’s reads and writes of one sequence’s state are on each channel.

The tensors are the weight image’s (super::image::image_of): each tensor’s tiles dealt to the channels from line 0, streamed by tensor and row. Everything the layout places after them — the rotary tables, then every sequence’s region — is one logical space of 64-byte lines, cut into granules of PhysicalMap::granule lines (the engine plan’s state chunk, one value head’s memory) dealt round the channels: granule g goes to channel g mod 4, at that channel’s local line (g / 4) · G plus the line’s place in the granule, from line B, the first line past the weight image on every channel. At 64 data bytes a beat a local line is a channel line, B plus the local line; at all 72 each channel’s local lines are packed end to end, local line i at byte 72 · B + 64 · i, nine logical lines to eight of the channel’s, so a granule’s first and last bytes may share a channel line with the channel’s granule before or after it.

A run of logical bytes is one run of channel bytes on each channel it touches (PhysicalMap::runs): the granules of one channel within the run are consecutive local lines. The four patterns a job streams of a sequence — a conv ring’s row, one value head’s memory, a lazily flushed memory’s log entries, an attention block’s cache rows of positions 0..=p with their scales — are runs of the layout’s own addresses (PhysicalMap::ring_row, PhysicalMap::memory, PhysicalMap::log, PhysicalMap::cache), and each run a stream the DDR4 model prices (Run::stream).

The engine reaches the space through two ports that place every logical line as PhysicalMap::locate does: the card port (card_port_verilog), a line a request for the engine’s core, and the fast port (fast_port_verilog), whole lines in runs a descriptor for a hybrid engine’s fast side.

Structs

Compaction

The machine’s memory without the matrices its matvec jobs stream: each streamed tensor’s bytes, to the next line, taken out, and every other byte moved down by the bytes taken out below it. The hybrid engine’s flat space holds the memory so, and after it each streamed tensor’s stream entry (StreamEntry, STREAM_ENTRY_LINES lines) in the runs’ order; the tables give the reference engine every address placed so, a streamed tensor’s its entry’s.

PhysicalMap

A machine layout on the card’s channels.

Run

Logical bytes [first, first + bytes) of the space after the weights as one channel holds them: from channel byte at on.

Functions

card_port_verilog

logos_card_port.v: the engine’s memory port on the card’s channels, every logical line where the map puts it.

channel_mux_verilog

logos_channel_mux, several fast ports on the channels’ fast ports at once: each port’s descriptors and write lines through registers of its own in the order it gives them, each channel’s descriptors taken from its ports in turn, each read line and write’s done token given back to the port it is of, one port’s write lines on a channel at a time.

fast_port_verilog

logos_fast_port, a hybrid engine’s fast side’s memory port on the channels’ fast ports: whole logical lines read and written where the map puts them, consecutive lines of a channel one descriptor, the reads returned in order.

pipe_verilog

logos_pipe, a stream through one register for a path a floorplan stretches across the device: each word taken leaves a clock or more later, in order, a word a clock while the far side takes them, the near side’s ready a register.

read_credit_verilog

logos_read_credit, a reader’s lines of one channel through the channel multiplexer asked only as a buffer of its own can hold them: its descriptors asked in runs of at most 32 lines, every line back taken at once, the reader’s next line in a register. A reader whose channels step together — the streaming unit — reaches the multiplexer through one a channel, so the multiplexer never waits on it for a line.