pub const WPE_CARAVEL: WpeCaravel;Expand description
The shipped wiring: the pin plan, the 21 ns clock (47.62 MHz on user_clock2) and a 115200-baud host.
The clock is the engine’s own. Every float unit, the integer multiplier and the conversions are staged so no
stage holds more than one carry chain, leading-one search, barrel shift or compressor tree, and the macro is
hardened at this period (CaravelProject::macro_period_ns). The period is what the engine’s slow corner meets
(signoff_blocks::honest_period_ns): hardened at 18.5 ns and routed, its paths through a compare chain into the
control and out through a fanout tree missed setup at ss_100C_1v60 by 1.13 ns on extracted parasitics, where the
routing stage’s repairs had closed on global-route estimates; hardened at 16 ns, the paths from the frame cache’s
hit into the stall that freezes every register, and from blk_term_kind_r, had missed by 1.48 ns. The off-chip
memory follows it: the edge runs two engine cycles per SCLK half, so the 42 ns half period still covers a read’s
round trip through the harness and the board (WpeCaravel::read_round_trip_ps).