Module terminal_rtl 

The Fabric Terminal’s RTL, emitted from its templates (codegen_sva/terminal/) with every protocol byte and dimension filled from super::terminal_protocol: the UART, SLIP framing, the PS/2 port, the VGA text plane, the link controller, the activity panel and the Nexys A7-100T top with its pins; and render, the picture the screen’s frames are held to. The board build reads the emitted files (board_files) from benchmarks/silicon/, where fabric_terminal --emit writes them.

Structs

Panel

What one frame of the activity panel shows: the engine’s state at the frame’s snapshot, and the engine clocks each block and each cell ran in the frame before it.

Screen

What the text plane is told to draw: every cell, the cursor and the pointer, the flash phase that blinking cells and the cursor follow, and the activity panel when the top has an engine.

Constants

ENGINE_FILE

The file board_files emits the engine into, beside the terminal’s other files.

ENGINE_MODULE

The fabric engine the Fabric Terminal instantiates: Board B’s deployed engine, with its probes.

FONT_HEX

The font ROM the text plane reads with $readmemh, one glyph row per line (see scripts/dev/gen-terminal-font.py).

FONT_LICENSE

The font’s license, which travels with the ROM.

Functions

board_files

Every file the board build reads from benchmarks/silicon/, as (file name, contents): the modules, the font ROM and its license, the pin constraints, the probed engine, and two tops — nexys_fabric_terminal with the engine and nexys_terminal_shell, the screen, keyboard and link alone.

font

The font ROM as bytes: glyph g, row r is font()[g * 16 + r], the MSB its leftmost pixel.

font8

The small font ROM, made from font: glyph g, row r is font8()[g * 8 + r], row terminal_protocol::FONT8_ROWS[r] of the 8×16 glyph.

modules

The module files a terminal top instantiates, in dependency order: (file name, filled Verilog). The activity panel belongs to a top with an engine.

render

The picture the screen draws for screen: 640 × 480 pixels, row-major, each the 12-bit 0xRGB the board’s DAC is driven with — the text plane (the small-text window in the small font), and the activity panel over it. This is the model the RTL’s rendered frames are held to.

top

The board top top: with engine naming the fabric engine module it instantiates — an engine emitted with its probes (emit_wprog_engine_soc_verilog_hw_probed), built beside it — or without one: the screen, keyboard and link alone, where ENGINE bytes are taken and dropped and the panel is not drawn.

xdc

The board’s pin constraints for any terminal top.