Module simt_ports 

simt_ports — the SIMT engine’s step on ports: its uniforms, its mask and every lane’s varying as inputs, every lane’s output and the warp-reduce as outputs, a step every clock. Where the engine’s register file (emit_gpu_simt_verilog) takes a step’s operands a slot a clock and hands its results back a read at a time, this takes them all at once, as a caller holding them in registers presents them, and reads no register of its own on the way in.

Each lane of the a·x + b kernel computes a·x as an aligned tree of adds (mul_tree), registered after the levels cut names, while b and the mask ride registers beside it. The clock after the product, each lane’s masked a·x + b is registered (a masked lane yields 0); the clock after that, the warp-reduce of those is registered and every lane output with it. A step’s results are on the outputs tree latency + 2 clocks after its operands.

Structs

SimtPorts

A ports engine’s RTL and the clocks from a step’s operands to its results.

Functions

emit_simt_ports_verilog

Emit eng’s step on ports as module name: inputs clk, a, b, mask (when the engine is predicated) and x0.., outputs y0.. and reduced (when it reduces). Refused unless the lane kernel computes a·x + b with a and b uniform and x per lane, and its reduce, if any, is an Add, Or, Xor or And: those fold a tree of lanes to the same word as the engine’s fold from the op’s identity.