Function emit_gpu_simt_verilog 

pub fn emit_gpu_simt_verilog(name: &str, eng: &SimtEngine) -> String

Emit the SIMT engine as synthesizable RTL: a narrow streaming interface (a 64-bit din loaded slot-by-slot into an internal lane register file, a go pulse that runs ALL lanes in one cycle — the spatial SIMT step — and a dout read back by raddr) wrapped around N verbatim copies of the certified kernel, with per-lane predication and an optional warp-reduce. Module name gpu_{name}. Readback: raddr in 0..N selects a lane output; raddr == N selects the reduced scalar (when a reduce is present).