Module rtl_extract 

Verilog Declaration Parser

Extracts module structure from Verilog/SystemVerilog source: module name, ports (direction, width), internal signals, parameters, and clock detection from always @(posedge/negedge) blocks.

This is NOT a full Verilog parser — it handles declaration-level extraction for hardware verification KG construction.

Structs

RtlModule

Extracted module structure.

RtlParam

A parameter declaration.

RtlParseError

Parse error.

RtlPort

A port in the module declaration.

RtlSignal

An internal signal declaration.

Enums

PortDirection

Port direction.

SignalType

Signal type.

Functions

parse_verilog_module

Parse a Verilog module declaration and extract its structure.