Module preflight 

Whether a persona build fits the card’s partial-reconfiguration region and can close its clock, decided before Quartus runs, from what the build ledger has measured.

A design is read as the timing model reads it (Design::of a TimingGraph): its mapped area, its deepest register-to-register path and its loop bound. The ALUTs it will take are the calibration’s area fit of that area (AreaFit); the ALMs, the larger of those ALUTs and its registers each at the ratio Quartus’s own syntheses in the ledger packed theirs (packing); the DSP blocks, the model’s halves paired, an upper bound, since Quartus maps some small products to logic. The capacity is the region the ledger’s last persona was placed in (capacity). A design over the region’s ALMs, DSP blocks or registers is refused; one past the fullest persona that has fit, and still inside the region, is tight. The deepest path must fit the period, and so must the loop bound, which no retiming can cut; a loop through no register is refused outright. A design whose parts step at different rates (an engine core stepping once in many clocks under a multicycle constraint beside a side stepping every clock) is held to its area whole and timed part by part (preflight_domains), each part’s paths given its cycles of the period. The fitter’s time is predicted from the personas’ own, a power law fitted to their ALMs. A verdict that has no measurement to rest on (no area fit, no region) is a refusal too.

Structs

Capacity

What a persona may use: the region the ledger’s last persona was placed in, and that compile’s name.

Design

A design as the timing model reads it: its area, its deepest path and its loop bound, in the model’s unit.

Holds

A design’s or a device’s ALMs, DSP blocks and M20K blocks.

Packing

How Quartus packs a synthesis into ALMs: the ALMs an ALUT takes, over the syntheses their ALUTs set, and the ALMs a register takes, over the syntheses their registers set (none when the ledger records no such synthesis).

PartTiming

One timed part’s figures.

Predicted

What a design is predicted to take and how fast it can run.

Preflight

A design’s preflight: what it is predicted to take, the region it is held to, every refusal, and every way it is tight without being refused.

Target

The clock a design must close: its period, and the nanoseconds one unit of the model’s delay takes on the card.

Timed

A part of a design timed on its own: its name, its design, and the periods its paths have.

Enums

DesignError

Why a timing graph is no design: one the model could not time, or not a graph.

LoopBound

The loop bound of a design: no loop, a loop through no register, or the most delay a register a loop holds.

Refusal

Why a design is not built.

Constants

DEVICE

What the D5005’s device holds: the 1SX280’s ALMs, DSP blocks and M20Ks.

Functions

alms_per_alut

The ALMs Quartus packs an ALUT into (packing’s, over the syntheses their ALUTs set).

capacity

The PR region of the last persona compile the ledger records with one.

device_library

The device primitives verilog instantiates and does not define, each declared as the box it is: the card’s floating-point DSP block (fourteennm_fp_mac, super::fp_oracle::fp_mac_blackbox), which only Quartus elaborates.

fitter_seconds

The fitter’s time for a persona of alms ALMs: seconds = a × alms^b, least squares in logs over every persona fit the ledger records with its region and fitter time; none without two of different sizes.

fullest

The fullest persona that fit: the passed compile whose region needed the most ALMs, and those ALMs.

over

Each resource needs takes past what device holds, named.

packing

The packing every synthesis the ledger records from one Verilog file shows: each synthesis’s estimated ALMs over its top’s ALUTs and registers, each synthesis set by the term the larger packing gives it (first by which it holds more of), each packing the geometric mean over the syntheses it sets, settled when no synthesis changes side.

preflight

The preflight of design against what ledger and calibration measured, at target, timed whole a period a path.

preflight_domains

The preflight of a design of area, each of its parts timed on its own at its cycles of target’s period.

synthesized_holds

What a synthesized flat image needs of the device, from its synthesis report: the ALMs and DSP blocks its partitions’ estimates sum to, and the M20K blocks the fitter gives its memories (floorplan::Ram::m20k, every partition’s), not its block memory bits over a block’s 20,480: a stack of blocks a power of two deep, and a byte-enabled block’s 32 bits, take more blocks than the bits do. None when the report gives no partition’s ALMs or DSP blocks.