pub fn packing(ledger: &Ledger) -> Option<Packing>Expand description
The packing every synthesis the ledger records from one Verilog file shows: each synthesis’s estimated ALMs over its top’s ALUTs and registers, each synthesis set by the term the larger packing gives it (first by which it holds more of), each packing the geometric mean over the syntheses it sets, settled when no synthesis changes side.