Struct PlasticineTarget 

pub struct PlasticineTarget {

    pub base: FabricTarget,
    pub pcu_rows: usize,
    pub pcu_cols: usize,
    pub pcu_lanes: usize,
    pub pcu_stages: usize,
    pub pcu_regs_per_stage: usize,
    pub pcu_scalar_io: (usize, usize),
    pub pcu_vector_io: (usize, usize),
    pub pmu_vector_io: (usize, usize),
    pub pcu_control_io: Option<(usize, usize)>,
    pub pcu_counters: Option<usize>,
    pub pmu_banks: usize,
    pub pmu_kib: usize,
    pub pmu_stages: usize,
    pub dram: DramSpec,
    pub clock_ghz: f64,
    pub area_mm2: f64,
    pub power_w: Option<f64>,
    pub peak_fp32_tflops: f64,
    pub cite: &'static str,
    /* private fields */
}

A published Plasticine mesh configuration.

Fields

base: FabricTarget

The certified per-PCU datapath descriptor (capabilities, precision, placement envelope).

pcu_rows: usize

Checkerboard array dimensions (PCUs and PMUs alternate 1:1).

pcu_cols: usize

pcu_lanes: usize

SIMD lanes per PCU.

pcu_stages: usize

FU pipeline stages per PCU.

pcu_regs_per_stage: usize

Pipeline registers per stage.

pcu_scalar_io: (usize, usize)

Scalar / vector / control ports per PCU (in, out).

pcu_vector_io: (usize, usize)

pmu_vector_io: (usize, usize)

PMU vector ports (in, out) — how many vector nets a scratchpad can sink / source at once.

pcu_control_io: Option<(usize, usize)>

pcu_counters: Option<usize>

Counter-chain depth per PCU, when the paper tabulates it.

pmu_banks: usize

Scratchpad banks per PMU, PMU capacity in KiB, PMU address-datapath stages.

pmu_kib: usize

pmu_stages: usize

dram: DramSpec

clock_ghz: f64

area_mm2: f64

power_w: Option<f64>

peak_fp32_tflops: f64

Published peak fp32 throughput (the chip’s native format; it has no bf16 datapath).

cite: &'static str

Where every number above comes from.

Implementations

impl PlasticineTarget

pub fn isca17() -> PlasticineTarget

ISCA 2017 Plasticine (Table 3 + §3–4): 16×8 checkerboard (64 PCU + 64 PMU), PCU 16 lanes × 6 stages × 6 registers, 6/5 scalar and 3/3 vector ports; PMU 16 banks × 16 KB = 256 KB, 4 stages, 3 vector in / 1 vector out; 4 × DDR3-1600 = 51.2 GB/s; 1 GHz; 112.8 mm² at 28 nm; 49 W; 12.3 fp32 TFLOPS.

pub fn sara_20x20() -> PlasticineTarget

The SARA / Capstan-era configuration (Zhang, Scaling a Reconfigurable Dataflow Accelerator, Stanford 2020, Table 3.3 + §4; Rucker et al., Capstan, MICRO 2021, Table 7): 20×20 checkerboard, PCU 16 lanes × 6 stages × 8 registers, 6/6 vector, 6/6 scalar, 16/8 control ports; PMU 16 banks × 256 KB, 10 stages; HBM2 at 1 TB/s; 352 mm² at 28 nm. Peak fp32 scales with the PCU count (200/64 × 12.3).

pub fn tungsten_20x20_ddr4() -> PlasticineTarget

The mesh the public toolchain simulates by default: PIR’s --row=20 --col=20 checkerboard (the SARA unit shapes) in front of Tungsten’s ramulator memory — DDR4-2133, 4 channels, DDR4_8Gb_x16 (DDR4-config.cfg in every generated app). Its effective bandwidth is what Tungsten itself reports on a memory-bound run (Average DRAM Read Bandwidth: 86.57 GB/s on Spatial’s DotProduct_0, recorded in benchmarks/silicon/plasticine_toolchain.json), used as the roofline of the rows calibrated against it.

pub fn rdu(chip: RduChip) -> PlasticineTarget

The SambaNova RDU — SN40L or SN50 — as a mesh descriptor, derived from RduChipFacts: the per-PCU envelope is the facts’ fabric target (rdu_shaped() / sn50_shaped(), every published number and its citation there); the checkerboard lays the facts’ PCU count out on the unit model’s column aspect (40 × 26 PCUs interleaved 1:1 with PMUs = 52 × 40 units); lanes, stages, banks, address stages and the counter chain read the unit model; the per-PMU capacity is the published SRAM spread over the PMU count; the DRAM is the published HBM at a MODELED rate; the clock, the area, the port counts and the register depth are modeled (cited on Self::rdu_provenance); power is not public (None); fp32 is not published, so the published bf16 peak stands as the roofline and says so. The mesh descriptor is therefore modeled through and through — the published facts live on the envelope.

pub fn sn40l_rdu() -> PlasticineTarget

The SN40L mesh descriptor (Self::rdu on RduChip::Sn40l).

pub fn sn50_rdu() -> PlasticineTarget

The SN50 mesh descriptor (Self::rdu on RduChip::Sn50).

pub fn rdu_provenance(chip: RduChip) -> Vec<(&'static str, Fact<f64>)>

Every numeric field of the RDU mesh descriptor with its provenance, by serialized path (the wrapped envelope’s numbers are the facts’ own and are ledgered there): the value the descriptor carries, and whether it is published or modeled, with the source or the gap it fills. Read by rdu_loop_lane_lock through reflection over the serialized descriptor, so a number without a row cannot land.

pub fn roofs(&self) -> Roofs

The configuration’s roofs: its DRAM bandwidth, clock and fp32 peak, each with what vouches for it.

pub fn pcus(&self) -> usize

PCUs in the mesh (a 1:1 checkerboard holds as many PMUs).

pub fn pmus(&self) -> usize

PMUs in the mesh.

pub fn scratchpad_kib(&self) -> usize

Total scratchpad in KiB (PMU count × PMU capacity).

Methods from Deref<Target = FabricTarget>

pub fn provides(&self, cap: Capability) -> bool

Whether this target provides a required capability.

pub fn require_cells(&self, cells: &[LoopCell]) -> Result<(), Unplaceable>

The capability half of place_with_target: every cell’s required capability is provided, or the FIRST missing one is named. A program larger than one datapath envelope (a whole decision program spanning many PCUs) is gated here cell by cell; its geometry is the mesh’s question.

pub fn require_gemm( &self, dataflow: Dataflow, precision: Precision, ) -> Result<(), Unplaceable>

Gate a requested (dataflow, precision) GEMM against this target — the check Phase-1+ lowerings call before placing a systolic/precision datapath. Returns a typed Unplaceable::MissingCapability naming the FIRST dial the target lacks (dataflow before precision), or Ok(()) if both are provided.

Trait Implementations

impl Clone for PlasticineTarget

fn clone(&self) -> PlasticineTarget

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for PlasticineTarget

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for PlasticineTarget

type Target = FabricTarget

The resulting type after dereferencing.

fn deref(&self) -> &FabricTarget

Dereferences the value.

impl PartialEq for PlasticineTarget

fn eq(&self, other: &PlasticineTarget) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Serialize for PlasticineTarget

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.

impl StructuralPartialEq for PlasticineTarget