Function mul_tree 

pub fn mul_tree(
    prefix: &str,
    a: &str,
    x: &str,
    width: u32,
    cut: impl Fn(usize) -> bool,
) -> MulTree

The product a · x mod 2^width of the width-bit Verilog expressions a and x, its signals named after prefix, registered after each level level for which cut(level) holds (the last level’s sum is the product).