Module mul_tree 

mul_tree — a word multiply as an aligned tree of adds. The product a · x mod 2^w is the sum of the w partial products x[i] ? a << i : 0; the tree adds them pairwise, level by level, each add only as wide as the bits it can still change (a partial product shifted by i is zero below bit i, and nothing above bit w − 1 survives), and a register can follow any level. On a fabric with carry chains every add is one chain and nothing multiplies; cut after every level, no stage holds more than one add.

Structs

MulTree

The tree of one multiply: its declarations and combinational assignments, its registers with the value each takes every clock, the signal holding the product after the last level, and the clocks from its operands to it.

Functions

mul_tree

The product a · x mod 2^width of the width-bit Verilog expressions a and x, its signals named after prefix, registered after each level level for which cut(level) holds (the last level’s sum is the product).

mul_tree_levels

The levels of the tree over width partial products: the pairwise adds that bring them down to one.