pub fn ddr2_files() -> Vec<(&'static str, String)>Expand description
The DDR2 controller, hart_ddr2, with DDR2_PARAMS written from super::ddr2::verilog_params for the board’s
part, and its Artix-7 PHY, hart_ddr2_phy (device primitives: the board’s build reads it, simulations do not).