Module rtl 

The hart’s RTL, as Verilog source files the board image and the simulations read. The hart is held to super::model (and its decompressor to super::rvc) by hart_rtl_lock; the computer around it, to the board model super::soc::Board by hart_soc_lock; the DDR2 controller, to the part’s data sheet by hart_ddr2_lock.

Constants

DDR2_PARAMS

The DDR2’s parameters, which the controller includes.

DEFINES

The memory map’s defines, which the computer’s files include.

Functions

board_files

What the board’s top adds around the computer and its DDR2: the queue that carries bytes between the hart’s clock and the terminal’s.

bringup_files

The bring-up image: the computer alone on Board B (hart_bringup_top), booting from the flash with its log on the USB UART — board_files, the log UART’s transmitter, the top and its pins.

core_files

The hart itself: (file name, source).

cpu_files

The hart with its caches, hart_cpu: the hart’s files, the instruction and data caches, their one way to memory, and the maintenance (fence.i, restart) they share.

ddr2_files

The DDR2 controller, hart_ddr2, with DDR2_PARAMS written from super::ddr2::verilog_params for the board’s part, and its Artix-7 PHY, hart_ddr2_phy (device primitives: the board’s build reads it, simulations do not).

fingerprint

A bitstream’s fingerprint — what a boot image is built for, and what SYS_RTL_MD5 reports: the md5 of every file the bitstream is built from, in order, then of the boot ROM’s words, so a changed ROM is another bitstream too.

fingerprint_words

A fingerprint as the SoC’s RTL_MD5_LO / RTL_MD5_HI parameters take it: the words SYS_RTL_MD5_LO and SYS_RTL_MD5_HI read as, its bytes little-endian.

loopback_files

The DDR2 PHY’s board probe, hart_ddr2_loopback_top: the PHY driving its own pads with the DDR2 held idle and sending what it reads back on the UART; its pins are the bring-up image’s, those its ports use.

rom_hex

The boot ROM as the $readmemh words its block RAM starts with: a 64-bit little-endian word a line, zeros to the ROM’s end.

soc_files

The whole computer, hart_soc: cpu_files, the boot ROM, the scratch RAM, the device registers, and DEFINES written from soc::verilog_defines. The boot ROM’s contents come from the ROM_INIT file the build names (rom_hex).