Module model 

The executable specification of the hart: an RV64IMAC processor with the Zicsr and Zifencei extensions, machine and user modes and eight physical-memory-protection entries, one architectural step at a time. The hart’s RTL is held to this model instruction by instruction, and this model is held to the RISC-V architecture tests and to qemu-riscv64.

What the hart leaves to software, by design: there is no floating-point unit, so every F and D instruction (and every access to fflags, frm or fcsr) is an illegal instruction the machine-mode firmware emulates; and a misaligned load, store or atomic traps with its address in mtval rather than being split in hardware. Neither occurs often enough in the compiler to matter: the measured floating-point share of a compile is 0.0002% of its instructions.

Structs

BusError

A physical access the bus refuses (no device at the address).

Hart

The architectural state of the hart.

Region

A range of physical addresses and what it may be used for: its physical memory attributes. An access outside every region, or one its region does not permit, is an access fault before it reaches the bus — so a device register is never fetched from, never the target of an atomic, and never read or written in part. These attributes are the only source of access faults: every access they permit, the bus completes.

Trap

A synchronous exception: its mcause and the value mtval receives.

Enums

Privilege

A privilege mode.

Step

What one step did.

Constants

CAUSE_BREAKPOINT

CAUSE_FETCH_ACCESS

CAUSE_ILLEGAL_INSTRUCTION

CAUSE_LOAD_ACCESS

CAUSE_MACHINE_ECALL

CAUSE_MISALIGNED_LOAD

CAUSE_MISALIGNED_STORE

CAUSE_STORE_ACCESS

CAUSE_USER_ECALL

MISA

misa: RV64 with the A, C, I, M and U extensions.

PMP_ENTRIES

The number of physical-memory-protection entries the hart implements; entries 8 to 15 read as zero.

Traits

Bus

The hart’s view of the system: naturally aligned reads and writes of 1, 2, 4 or 8 bytes.