Enum LaneArith 

pub enum LaneArith {
    Combinational,
    DecomposedFma {
        stages: usize,
    },
    SequentialFma {
        select_slice: usize,
    },
    Streamed {
        every: usize,
    },
}

The datapath multiply strategy for the lane’s a·x + b arithmetic — a first-class, tuneable, SAT-certified knob. Every strategy is functionally identical (a·x + b, 64-bit wrapping); they trade cycle count against physical (routing / antenna) friendliness.

Variants

Combinational

Per-op combinational body — the whole kernel evaluates in ONE cycle. A WIDE combinational *: fast (single-cycle) but met1-antenna-dense on Sky130.

DecomposedFma

The 64×64 multiply STRUCTURALLY split into three 32×32 partial products, pipelined over stages registered stages — real GPU-ALU pipelining. Smaller multipliers → shorter nets, but still a WIDE combinational * per partial product.

Fields

stages: usize

SequentialFma

A SEQUENTIAL shift-add multiply over the datapath width: ONE reused adder per lane, one bit of the multiplier consumed per cycle (WIDTH cycles). Bounded fan-out (like a word-serial multiplier) → NO wide * anywhere → antenna-trivial. Only valid for the a·x+b kernel.

select_slice is the fan-out / antenna knob. The per-cycle conditional-add partial product mp[0] ? mc : 0 is emitted as select_slice (* keep *) copies of the multiplier LSB, each gating its OWN WIDTH / select_slice-bit group of mc — so no single select net spiders across the full datapath (the met1-antenna root cause). SMALLER select_slice = each copy gates FEWER mux bits = lower fan-out = less antenna, at the cost of MORE (* keep *) wires; LARGER = the reverse. It MUST divide the datapath width evenly (WIDTH % select_slice == 0, asserted at emit time), so the byte-groups tile mc exactly with no dropped or misaligned bit.

Fields

select_slice: usize

Streamed

ONE multiply shared by every lane, an aligned tree of adds over the 64 partial products (mul_tree, no *) registered after every every-th level and after the last. Each lane’s a·x enters it in the clock the lane’s x is loaded, so the products stream out while the rest of the operands load; as each emerges its lane’s masked + b is registered and folded into the warp-reduce. Only valid for the a·x+b kernel with a per-lane x.

Fields

every: usize

Trait Implementations

impl Clone for LaneArith

fn clone(&self) -> LaneArith

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for LaneArith

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for LaneArith

fn eq(&self, other: &LaneArith) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for LaneArith