Module fp_hard 

The engine’s f32 multiply and add on the card’s floating-point DSP block (fourteennm_fp_mac), as the oracle (super::fp_oracle) measured it: a wrapper with the pipelined unit’s ports (logos_fmul_p’s and logos_fadd_p’s: clk, a, b, y) and exactly its latency, computing the engine’s own arithmetic (Semantics::ENGINE) on a block whose semantics are another member of the family, wherever a thin layer of logic around the block can make them one.

The block is registered fully, as the IP registers each mode, when that is no deeper than the latency, and with its output register alone otherwise; registers after it make up the rest (plan). Around it: a denormal operand read as a zero of its sign when the block keeps denormal operands, a denormal result written as a zero of its sign when the block keeps denormal results (a result rounded at the denormals’ precision and flushed unless it reaches the least normal, as the engine’s is), and every NaN result the engine’s 0x7fc00000 when the block returns another; a multiply’s denormal operand is decided beside the block rather than flushed before it, so the block multiplies the significands the engine’s multiply does. A block that flushes its results otherwise (tininess decided another way, or the flushed zero always positive) loses what no logic after it can restore, and is refused by name. hard_verilog writes the wrapper free-running; hard_verilog_ce writes it stepping at a clock enable, the block’s registers enabled with the rest.

Structs

Block

What the oracle measured of one mode of the block: the semantics it computes and its latency fully registered and with its output register alone.

Measurement

What the card said of its block: each mode’s semantics and depths, the multiply-add’s latency and rounding.

Plan

A wrapper’s build: the block’s registering, the registers after it, and what the logic around it corrects.

Tally

One mode’s counts as the measurement found them: each class’s steps differing from the block over every run, in the oracle’s order, and the steps no class explains.

Enums

HardError

Why a block cannot be the engine’s unit.

MeasureError

Why a measurement names no block.

Op

The two operations a block computes for the engine.

Registering

How the block is registered in a wrapper.

Rounding

How the block’s multiply-add rounds.

Functions

hard_verilog

The wrapper module for the block’s op at latency clocks, free-running.

hard_verilog_ce

The wrapper module for the block’s op at latency steps, every register (the block’s and the pads) stepping where step_en, as the engine’s enabled cores step.

hard_verilog_ce_for

hard_verilog_ce computing target (plan_for): hard_verilog_ce is this of Semantics::ENGINE, byte for byte.

hard_verilog_for

hard_verilog computing target (plan_for): hard_verilog is this of Semantics::ENGINE, byte for byte.

plan

The wrapper’s build for the block’s op at latency clocks, standing in for the engine’s own arithmetic (plan_for of Semantics::ENGINE).

plan_for

The wrapper’s build for the block’s op at latency clocks that makes it compute target: the logic around it flushes the denormal operands the block reads as themselves where target reads zeros, flushes the denormal results the block keeps where target flushes them at the denormals’ place keeping their sign, and writes 0x7fc00000 for every NaN where that is target’s one NaN and the block’s is another. Refused by name is a block that reads a zero or flushes a result where target keeps a denormal, decides tininess elsewhere than target, flushes to another sign, or returns NaNs target does not and the wrapper cannot write.