Struct DesignProfile 

pub struct DesignProfile {
    pub name: String,
    pub clock_port: String,
    pub clock_period_ns: f64,
    pub port_bits: u32,
    pub macros: Vec<String>,
    pub fixed_die: bool,
}

What the compiler knows about a design that changes how it should be built.

Fields

name: String

Top-level module name; also the OpenLane DESIGN_NAME.

clock_port: String

clock_period_ns: f64

port_bits: u32

Top-level I/O count. A design with many wide buses is PAD-LIMITED — its die is set by the perimeter its pins need, not by its logic — and must be given an explicit die area or the floorplanner sizes it too small for the pins to fit.

macros: Vec<String>

Hardened macros this design instantiates (SRAM, or another of our blocks).

fixed_die: bool

Set for a fixed-die shuttle vehicle wrapper, where the die is not ours to choose.

Implementations

impl DesignProfile

pub fn new(name: &str, clock_port: &str, clock_period_ns: f64) -> Self

pub fn with_ports(self, bits: u32) -> Self

pub fn is_pad_limited(&self) -> bool

A design is pad-limited when its perimeter, not its logic, sets the die. The threshold is the point at which the observed blocks needed an explicit DIE_AREA: the infinichip subsystem (~386 pins) did, everything smaller did not.

Trait Implementations

impl Clone for DesignProfile

fn clone(&self) -> DesignProfile

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for DesignProfile

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for DesignProfile

fn eq(&self, other: &DesignProfile) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for DesignProfile