Function emit_loop_fabric_verilog_pipelined 

pub fn emit_loop_fabric_verilog_pipelined(
    name: &str,
    lf: &LoopFabric,
    mul_bits: Option<u32>,
    term_budget: f64,
) -> Result<PipelinedLoop, String>

Emit the counted-loop CGRA with every accumulator in carry-save form and its terms pipelined ahead of it.

A loop whose state registers each take s_j ← s_j + Σ ±terms, with no term reading any state, carries only two recurrences: the induction counter and the accumulators. The terms (operand arithmetic and the multiplies) compute from the counter and the invariants through as many register stages as term_budget (in the units of loop_cell_delay) asks, each tile in the earliest stage its operands and the budget allow; the counter is delayed to every stage that reads it, and a valid flag travels with each iteration. On the edge after the last term stage each accumulator’s sum and carry words absorb the terms through a tree of 3:2 compressors, so the recurrence holds no carry chain. The counter increments through a parallel-prefix AND. The result is the sum of the result register’s two words, a loop whose body runs finishes PipelinedLoop::term_stages clocks after the counter does, and every other behaviour is emit_loop_fabric_verilog_int8’s (with mul_bits) or emit_loop_fabric_verilog’s.

Refused, with the reason, for a loop with a sequence input, a heap island, an epilogue, a functional-unit tile, or a state that is not such an accumulator.