pub enum CellKind {
Arith(AluOp, Src2, Src2),
Select(CmpKind, Src2, Src2, Src2, Src2),
Func(FuncUnit, Src2, Src2),
Simd(VecOp, LaneTy, Src2, Src2),
Mem(MemOp, Src2, Src2),
}Expand description
A tile’s optional compute: an arithmetic op or a predicated select over its visible sources.
Variants§
Arith(AluOp, Src2, Src2)
Select(CmpKind, Src2, Src2, Src2, Src2)
Func(FuncUnit, Src2, Src2)
A FUNCTIONAL-UNIT tile — division/mod/floor-div, magic-reciprocal high-multiply, power, or a float op
(FuncUnit). Combinational at the RTL level (a synthesized divider / the FPU’s combinational form), so
it settles in the same 1-clock feed-forward pass as Arith — but it is NOT SAT-lowered (bitblast has
no bvsdiv/bvsrem), so a Func-bearing grid is proven by eval_grid ≡ VM + iverilog, exactly as the
decision fabric proves division (emit_decision_fabric_verilog + microprice_rtl_matches_vm_under_iverilog).
Simd(VecOp, LaneTy, Src2, Src2)
A packed-SIMD tile — a VecOp (add / bitwise) over two operands, computed lane-wise for the given
LaneTy (Add = the carry-isolated SWAR form). Combinational, so it settles in the same 1-clock pass
as Arith; but it is NOT SAT-lowered here (proven ≡ lane-wise by simd_tile_lock + iverilog), so a
Simd-bearing grid is combinational-for-emission yet refused by the reconfig SAT (like Func).
Mem(MemOp, Src2, Src2)
A MEMORY (state-plane) tile — a read/write/alloc against ONE shared heap that all Mem tiles access
(the dmem-style block RAM the soft-core already carries). The heap mirrors the VM/model layout
([len, e0..eN]), so collections/structs/text/CRDT compose from Mem + Arith tiles exactly as the
whole-program model (fabric_rtl.rs exec_ops) does. Stateful (a synchronous BRAM), so it is NOT
SAT-lowered and is NOT combinational — proven by eval_grid_with_heap ≡ the model ≡ VM + iverilog.
The tile’s two Src2 operands are (A, B): HeapRead reads heap[A], HeapWrite does heap[A] = B
and drives B, HeapAlloc grows the heap by A words and drives the new base pointer.
Trait Implementations§
Auto Trait Implementations§
impl Freeze for CellKind
impl RefUnwindSafe for CellKind
impl Send for CellKind
impl Sync for CellKind
impl Unpin for CellKind
impl UnsafeUnpin for CellKind
impl UnwindSafe for CellKind
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
§impl<T> Downcast for Twhere
T: Any,
impl<T> Downcast for Twhere
T: Any,
§fn into_any(self: Box<T>) -> Box<dyn Any>
fn into_any(self: Box<T>) -> Box<dyn Any>
Box<dyn Trait> (where Trait: Downcast) to Box<dyn Any>. Box<dyn Any> can
then be further downcast into Box<ConcreteType> where ConcreteType implements Trait.§fn into_any_rc(self: Rc<T>) -> Rc<dyn Any>
fn into_any_rc(self: Rc<T>) -> Rc<dyn Any>
Rc<Trait> (where Trait: Downcast) to Rc<Any>. Rc<Any> can then be
further downcast into Rc<ConcreteType> where ConcreteType implements Trait.§fn as_any(&self) -> &(dyn Any + 'static)
fn as_any(&self) -> &(dyn Any + 'static)
&Trait (where Trait: Downcast) to &Any. This is needed since Rust cannot
generate &Any’s vtable from &Trait’s.§fn as_any_mut(&mut self) -> &mut (dyn Any + 'static)
fn as_any_mut(&mut self) -> &mut (dyn Any + 'static)
&mut Trait (where Trait: Downcast) to &Any. This is needed since Rust cannot
generate &mut Any’s vtable from &mut Trait’s.