Struct Ddr4Grade 

pub struct Ddr4Grade {

    pub part: &'static str,
    pub bank_groups: u32,
    pub banks_per_group: u32,
    pub row_bits: u32,
    pub col_bits: u32,
    pub dq_bits: u32,
    pub rate: u64,
    pub mem_mhz: u64,
    pub cl: u64,
    pub cwl: u64,
    pub pl: u64,
    pub trcd_ps: u64,
    pub trp_ps: u64,
    pub tras_ps: u64,
    pub trc_ps: Option<u64>,
    pub trrd_s_ck: u64,
    pub trrd_l_ck: u64,
    pub tfaw_ps: u64,
    pub tccd_s_ck: u64,
    pub tccd_l_ck: u64,
    pub twr_ps: u64,
    pub twtr_s_ck: u64,
    pub twtr_l_ck: u64,
    pub trtp_ps: u64,
    pub trfc_ps: u64,
    pub trefi_ps: u64,
}

A DDR4 channel as its controller is configured: geometry, latencies and timing minimums (picoseconds unless named in clocks).

Fields

part: &'static str

bank_groups: u32

banks_per_group: u32

row_bits: u32

col_bits: u32

dq_bits: u32

Data bits the channel carries a transfer.

rate: u64

Memory clocks a controller clock spans: a controller-side word is one burst.

mem_mhz: u64

cl: u64

cwl: u64

pl: u64

Command-address parity latency, added to both latencies.

trcd_ps: u64

trp_ps: u64

tras_ps: u64

trc_ps: Option<u64>

ACT to ACT in one bank; None for tRAS + tRP.

trrd_s_ck: u64

trrd_l_ck: u64

tfaw_ps: u64

tccd_s_ck: u64

tccd_l_ck: u64

twr_ps: u64

twtr_s_ck: u64

twtr_l_ck: u64

trtp_ps: u64

trfc_ps: u64

trefi_ps: u64

Implementations

impl Ddr4Grade

pub const D5005_EMIF: Ddr4Grade

One memory channel of the Intel PAC D5005 as its OFS shell configures it (D5005_EMIF_IP): a single-rank RDIMM of x8 devices (MEM_DDR4_FORMAT_ENUM MEM_FORMAT_RDIMM, MEM_DDR4_RANKS_PER_DIMM 1, MEM_DDR4_DQ_PER_DQS 8), 72 bits wide (MEM_DDR4_DQ_WIDTH 72); 4 bank groups of 4 banks (MEM_DDR4_BANK_GROUP_WIDTH 2, MEM_DDR4_BANK_ADDR_WIDTH 2), 2^16 rows (MEM_DDR4_ROW_ADDR_WIDTH 16) of 2^10 columns (MEM_DDR4_COL_ADDR_WIDTH 10); DDR4-2400 (MEM_DDR4_SPEEDBIN_ENUM DDR4_SPEEDBIN_2400) at 1200 MHz (PHY_DDR4_MEM_CLK_FREQ_MHZ 1200.0) under a quarter-rate controller (PHY_DDR4_RATE_ENUM RATE_QUARTER); CL 21 (MEM_DDR4_TCL), CWL 16 (MEM_DDR4_WTCL), parity latency 4 (MEM_DDR4_AC_PARITY_LATENCY DDR4_AC_PARITY_LATENCY_4); tRCD and tRP 14.16 ns, tRAS 32 ns, tFAW 21 ns, tWR 15 ns, tRFC 350 ns, tREFI 7.8 µs (MEM_DDR4_TRCD_NS, _TRP_NS, _TRAS_NS, _TFAW_NS, _TWR_NS, _TRFC_NS, _TREFI_US); tRRD_S 4, tRRD_L 6, tCCD_S 4, tCCD_L 6, tWTR_S 3, tWTR_L 9 clocks (MEM_DDR4_TRRD_S_CYC, _TRRD_L_CYC, _TCCD_S_CYC, _TCCD_L_CYC, _TWTR_S_CYC, _TWTR_L_CYC). The configuration names no tRTP: it is JESD79-4’s minimum, the larger of 4 clocks and 7.5 ns.

pub fn at(&self) -> Ddr4Timing

The configuration clocked: every picosecond minimum in whole memory clocks, rounded up.

Trait Implementations

impl Clone for Ddr4Grade

fn clone(&self) -> Ddr4Grade

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Ddr4Grade

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for Ddr4Grade

fn eq(&self, other: &Ddr4Grade) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Serialize for Ddr4Grade

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.

impl Copy for Ddr4Grade

impl Eq for Ddr4Grade

impl StructuralPartialEq for Ddr4Grade