Function verilog_model 

pub fn verilog_model(t: &Ddr4Timing, lookahead: usize) -> String

A DDR4 channel behind an Avalon-MM slave for simulation, scheduled by this module’s controller model: every line a burst brings is issued as Scheduler::line_at issues it at the memory clock the slave takes it (four to a controller clock), a write’s data is stored as it is taken, and a read’s data, as the memory held it when the read was taken, returns in order PIPE controller clocks after the controller clock its burst leaves the data bus in. With LOG set it writes, to <LOGFILE>_<ID>.log, every line it schedules (L line write arrive column) and every command it places (C clock kind group bank row-or-column, the kind an index of LOGGED_KINDS).