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emit_litedram_traffic_testbench

logicaffeine_compile::codegen_sva::ddr2_traffic

Function emit_litedram_traffic_testbench 

Source 
pub fn emit_litedram_traffic_testbench(
    t: &Ddr2Timing,
    traffic: &Traffic,
) -> String
Expand description

tb_qor_dram for LiteDRAM: the stream through the native port of litedram_ctrl, the controller exactly as the bench synthesises it, its DFI wired to litedram_phy_model, LiteDRAM’s own SDRAMPHYModel (both from litedram_controller.py); one command a word, write data offered for every accepted write in order, read data always accepted, reads presented as for ddr2_ctrl. The system clock runs at half the DRAM clock, and the log counts DRAM clocks: DFI phase p of system clock k is DRAM clock 2k + p, a request presented or accepted at system clock k is logged at 2k. It reads words.hex and writes dram.log.