Module ddr2_traffic 

ddr2_traffic — the K7 traffic: one stream of 64-bit words that every DDR2 controller of the comparative bench writes to the same part and reads back, the device and testbenches it runs on, and the judgement of a run’s log.

The stream is words, not any controller’s requests. A word index is LiteDRAM’s native-port address under ROW_BANK_COL, and place puts it in a bank, a row and four x16 columns. Each controller carries the stream through its own request interface — whole words, or a 16-bit port’s four parts — and its testbench logs every command the bus carried, every request the controller accepted and every word it delivered. judge holds the bus to the JEDEC checker (super::ddr2_jedec::check_bus), matches each request to the column command that served it, checks that every word read back is the word written, and measures: request → column command latency, the stream’s span, and the bus’s.

The operating point is the Nexys A7’s DDR2, Micron MT47H64M16HR-25, at DDR2-400: the clock LiteDRAM’s controller drives it at from a 100 MHz system clock at 1:2, and a 1:1 controller from 200 MHz.

Structs

Controller

A controller the K7 traffic gate drives: its name in the K7 design table, the burst length its mode register sets, and how its requests carry a word.

Delivery

A word the controller delivered back.

Interface

How a controller’s requests carry a word: in parts requests, part p at the word’s first column plus p × cols_per_part.

Judgement

What a run measured. stream_cycles runs from the first accepted request to the last delivered word; payload_cycles is what the stream needs of an x16 DDR bus (two clocks a word, each way); bus_span runs from the first command to the last beat; row_hits counts column commands that found their row already open by an earlier column command; the write and read latencies run from a request’s acceptance to the column command that served it; read_service from the presentation of a word’s first read request to the word’s delivery, and read_bus to the last beat of the word’s read data on the DRAM bus — the same span without any PHY’s pipeline.

Log

A run’s log: the bus, the requests as presented and as accepted, the deliveries, and the closing line (its clock and the testbench’s error count). Clocks are DRAM clocks from the end of reset.

Place

Where a word lives: its bank, its row, and the first of its four x16 columns.

Request

A request the requester presented or the controller accepted: the clock, write or read, the word, and which part.

Stats

A latency distribution in DRAM clocks: count, extremes, nearest-rank median and 99th percentile, mean.

Traffic

The stream: words words written in order, then read back in the same order, each read presented as soon as the controller took the one before, or for the probe PROBE_EVERY clocks after it was presented.

Enums

Kind

Pattern

Constants

K7_CONTROLLERS

LOGOS’s ddr2_ctrl (a 16-bit request port, BL8), LOGOS’s ddr2_dfi_ctrl and LiteDRAM’s controller (each a 64-bit native port, BL4 at 1:2).

K7_GRADE

The K7 part.

K7_TCK_PS

The K7 DRAM clock period: DDR2-400.

PROBE_EVERY

The DRAM clocks between the probe’s reads: more than any K7 controller needs to serve one read with a refresh in its way, so each read meets the controller idle.

SCATTER_ROWS

The rows of every bank the scattered stream draws its words from.

Functions

emit_ddr2_ctrl_traffic_testbench

tb_qor_dram for ddr2_ctrl: the stream through its 16-bit request port, four requests a word (part p at column 4 × the column word + p), the device behind it at burst length t.bl with every beat but the addressed one masked. A request is presented as soon as the one before was taken; for the probe, a word’s first read waits until Traffic::every clocks after the word before’s, and the reads start two of those after the last write. It reads words.hex (Traffic::rom) and writes dram.log (read_log).

emit_ddr2_device_verilog

ddr2_device: the part as a testbench sees it through an ideal PHY. It keeps each bank’s open row and stores 16-bit columns for ROWB row-address bits; a WRITE takes its burst (with a per-beat mask, 1 = not written) on the command’s clock, a READ returns its burst CL clocks later, both in the sequential burst order that wraps within the burst’s aligned block. An ACT past the stored rows, or a column command to a bank with no open row, raises model_error. Bus timing is not its business: the log’s JEDEC checker holds the bus to the rules.

emit_ddr2_dfi_ctrl_traffic_testbench

tb_qor_dram for ddr2_dfi_ctrl: LiteDRAM’s testbench with the LOGOS controller in litedram_ctrl’s place, on the same native port and DFI, against the same SDRAMPHYModel; it has no stream framing (first/last) and no read back-pressure, which LiteDRAM’s crossbar does not read either.

emit_litedram_traffic_testbench

tb_qor_dram for LiteDRAM: the stream through the native port of litedram_ctrl, the controller exactly as the bench synthesises it, its DFI wired to litedram_phy_model, LiteDRAM’s own SDRAMPHYModel (both from litedram_controller.py); one command a word, write data offered for every accepted write in order, read data always accepted, reads presented as for ddr2_ctrl. The system clock runs at half the DRAM clock, and the log counts DRAM clocks: DFI phase p of system clock k is DRAM clock 2k + p, a request presented or accepted at system clock k is logged at 2k. It reads words.hex and writes dram.log.

judge

Judge a run of traffic through a controller with request interface iface, its bus held to t.

k7_controller

k7_ddr2_ctrl_verilog

ddr2_ctrl as the K7 bench builds, synthesises and drives it: the LOGOS DDR2 controller at the K7 part’s table, burst length 8.

k7_dfi_ctrl_verilog

ddr2_dfi_ctrl as the K7 bench builds, synthesises and drives it: the LOGOS DFI 1:2 controller at the K7 part’s rules, burst length 4.

k7_timing

The K7 part clocked at the K7 operating point, burst length bl.

place

The place of word w: ROW_BANK_COL, the column word in the low eight bits, the bank above, the row above that.

read_log

Read a log: C <clock> <cs#> <ras#> <cas#> <we#> <ba> <a>, P <clock> <W|R> <word> <part> (presented), Q <clock> <W|R> <word> <part> (accepted), D <clock> <word> <hex value>, END <clock> <errors>; blank lines pass.

word_value

The value written to word w: SplitMix64’s output for w, a bijection, so every word’s value is its own.