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emit_ddr2_dfi_ctrl_traffic_testbench

logicaffeine_compile::codegen_sva::ddr2_traffic

Function emit_ddr2_dfi_ctrl_traffic_testbench 

Source 
pub fn emit_ddr2_dfi_ctrl_traffic_testbench(
    t: &Ddr2Timing,
    traffic: &Traffic,
) -> String
Expand description

tb_qor_dram for ddr2_dfi_ctrl: LiteDRAM’s testbench with the LOGOS controller in litedram_ctrl’s place, on the same native port and DFI, against the same SDRAMPHYModel; it has no stream framing (first/last) and no read back-pressure, which LiteDRAM’s crossbar does not read either.