Function emit_ddr2_device_verilog 

pub fn emit_ddr2_device_verilog(t: &Ddr2Timing) -> String

ddr2_device: the part as a testbench sees it through an ideal PHY. It keeps each bank’s open row and stores 16-bit columns for ROWB row-address bits; a WRITE takes its burst (with a per-beat mask, 1 = not written) on the command’s clock, a READ returns its burst CL clocks later, both in the sequential burst order that wraps within the burst’s aligned block. An ACT past the stored rows, or a column command to a bank with no open row, raises model_error. Bus timing is not its business: the log’s JEDEC checker holds the bus to the rules.