pub fn emit_ddr2_ctrl_traffic_testbench(
t: &Ddr2Timing,
traffic: &Traffic,
) -> StringExpand description
tb_qor_dram for ddr2_ctrl: the stream through its 16-bit request port, four requests a word (part p at
column 4 × the column word + p), the device behind it at burst length t.bl with every beat but the addressed
one masked. A request is presented as soon as the one before was taken; for the probe, a word’s first read waits
until Traffic::every clocks after the word before’s, and the reads start two of those after the last write.
It reads words.hex (Traffic::rom) and writes dram.log (read_log).