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emit_ddr2_init_fsm_verilog

logicaffeine_compile::codegen_sva::ddr2_phy

Function emit_ddr2_init_fsm_verilog 

Source 
pub fn emit_ddr2_init_fsm_verilog(
    t: &DramTimings,
    cke_low_cycles: u64,
) -> String
Expand description

Emit ddr2_init_fsm — a ROM-driven power-up sequencer. The ROM is GENERATED from ddr2_init_sequence; the FSM drives {cke, cs_n, ras_n, cas_n, we_n, ba, a} per entry, waits its cycle count, advances, and latches init_done. (Behavioral iverilog validation lands with the controller-integration brick; this brick pins the ROM to the JEDEC spec.)