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emit_ddr2_bank_model_verilog

logicaffeine_compile::codegen_sva::ddr2_phy

Function emit_ddr2_bank_model_verilog 

Source 
pub fn emit_ddr2_bank_model_verilog(t: &DramTimings) -> String
Expand description

Emit ddr2_bank_model — a behavioral DDR2 array that stores/returns data (CL read latency) AND enforces tRCD/tRAS/tRP/tWR, raising model_error on any violation (the round-trip checker).