Module ddr2_phy 

ddr2_phy — a full custom hand-rolled DDR2 controller + PHY for the Nexys A7-100T’s on-board Micron MT47H64M16 (1 Gb, x16, 8 banks, DDR2-800). This is Phase 1 of the DRAM-into-Compute campaign: total ownership in the openXC7 flow (no vendor MIG), tied directly to the dram_executor command engine (super::dram), so the SAME command stream that drives the JEDEC-legal schedule also drives the deliberately-illegal ComputeDRAM cadences.

Built in gated, iverilog-verified sub-steps (each proven against a behavioral DDR2 model before the board): • 1a — command layer (THIS brick first): op field → DDR2 pins, single source of truth; clocking + I/O primitives (MMCM/PLL, SSTL18, ODDR/IDDR, IDELAY); • 1b — init / mode-register sequence; • 1c — closed-loop per-byte-lane read calibration; • 1d — full controller (ODT, refresh, power-down, bank-interleave, status); • 1e — memtest over the full 128 MiB (the Phase-1 gate).

The command layer maps the dram_executor op field (0=ACT 1=RD 2=WR 3=PRE 4=REFpb — see super::dram::delta_encode) plus the init commands (NOP / DESELECT / LOAD-MODE) to the JEDEC DDR2 command truth table on {CS#, RAS#, CAS#, WE#}. The Verilog ddr2_cmd_encoder is GENERATED from ddr2_pins, so the netlist and the model can never drift.

Enums

Ddr2Cmd

A DDR2 command (JEDEC truth table over {CS#, RAS#, CAS#, WE#}, with CKE held high).

InitStep

One step of the DDR2 power-up init sequence.

ModeReg

A DDR2 mode register, identified by its BA[1:0] selector.

Constants

EMR1_DLL_ENABLE

EMR1 with the DLL ENABLED (A0 = 0), full drive, ODT off, AL = 0, OCD exit — the first EMR1.

EMR1_OCD_DEFAULT

EMR1 OCD calibration DEFAULT (A9:A7 = 111).

EMR1_OCD_EXIT

EMR1 OCD calibration EXIT (A9:A7 = 000), DLL still enabled.

Functions

ddr2_init_sequence

The JEDEC DDR2 power-up init sequence for this part, as data. cke_low_cycles is the ≥200 µs power-up hold expressed in controller cycles (a deployment parameter of the chosen clock).

ddr2_pins

The (cs_n, ras_n, cas_n, we_n) pin levels for a DDR2 command — the JEDEC DDR2 command truth table. This is the SINGLE SOURCE OF TRUTH the Verilog encoder is generated from.

emit_ddr2_bank_model_verilog

Emit ddr2_bank_model — a behavioral DDR2 array that stores/returns data (CL read latency) AND enforces tRCD/tRAS/tRP/tWR, raising model_error on any violation (the round-trip checker).

emit_ddr2_cmd_encoder_testbench

A self-checking testbench for ddr2_cmd_encoder: drives every op with issue = 0 and issue = 1 and asserts the pins equal ddr2_pins (expectations GENERATED from the same truth table). PASS/FAIL.

emit_ddr2_command_encoder_verilog

Emit the combinational ddr2_cmd_encoder — op field + issue → DDR2 command pins. When issue is low the bus holds NOP (CS# low, RAS#/CAS#/WE# high). The case arms are GENERATED from ddr2_pins, so the netlist is by-construction consistent with the model/oracle.

emit_ddr2_controller_testbench

Emit tb_ddr2_ctrl — writes n_words (distinct bank/col addresses), reads them back, and asserts each read equals the written data with no model_error. The access pattern is generated here.

emit_ddr2_controller_verilog

Emit ddr2_ctrl — the request-driven DDR2 controller FSM (timings baked from the table).

emit_ddr2_init_fsm_verilog

Emit ddr2_init_fsm — a ROM-driven power-up sequencer. The ROM is GENERATED from ddr2_init_sequence; the FSM drives {cke, cs_n, ras_n, cas_n, we_n, ba, a} per entry, waits its cycle count, advances, and latches init_done. (Behavioral iverilog validation lands with the controller-integration brick; this brick pins the ROM to the JEDEC spec.)

emit_ddr2_init_testbench

A behavioral testbench for ddr2_init_fsm: a bus monitor records each isolated real command (NOP/DESELECT skipped) the FSM issues during power-up, and asserts the recorded log equals the JEDEC command sequence (generated from ddr2_init_sequence) and that init_done asserts.

emit_transaction

Emit the controller’s per-request command sequence for one closed-page DDR2 access.

executor_op_to_cmd

Map a dram_executor op field (0=ACT 1=RD 2=WR 3=PRE 4=REFpb) to its DDR2 command. Returns None for op codes outside the executor’s issued set.

init_rom_word

Pack an init step into the 44-bit ddr2_init_fsm ROM word {cke, cs_n, ras_n, cas_n, we_n, ba[1:0], a[12:0], wait[23:0]} — the SINGLE encoding shared by the emitter and the drift lock, with the command pins taken from ddr2_pins.

mr_opcode

Encode the Mode Register (BA = 00) opcode from the timing table: burst length (A2:A0), sequential burst type (A3 = 0), CAS latency (A6:A4, == tRCD on the 5-5-5 grade), DLL reset (A8), and write recovery WR-1 (A11:A9).