pub struct Ddr2Timing {Show 19 fields
pub grade: Ddr2Grade,
pub tck_ps: u64,
pub bl: u64,
pub cl: u64,
pub wl: u64,
pub trcd: u64,
pub trp: u64,
pub trpa: u64,
pub tras: u64,
pub tras_max: u64,
pub trc: u64,
pub trrd: u64,
pub tfaw: u64,
pub twr: u64,
pub twtr: u64,
pub trtp: u64,
pub trfc: u64,
pub trefi: u64,
pub tccd: u64,
}Expand description
A grade clocked: every rule in whole clocks. wl is cl − 1, trpa the precharge-all period.
Fields§
§grade: Ddr2Grade§tck_ps: u64§bl: u64§cl: u64§wl: u64§trcd: u64§trp: u64§trpa: u64§tras: u64§tras_max: u64§trc: u64§trrd: u64§tfaw: u64§twr: u64§twtr: u64§trtp: u64§trfc: u64§trefi: u64§tccd: u64Implementations§
Source§impl Ddr2Timing
impl Ddr2Timing
Sourcepub fn read_to_precharge(&self) -> u64
pub fn read_to_precharge(&self) -> u64
READ → PRECHARGE, same bank: AL + BL/2 − 2 + max(tRTP, 2).
Sourcepub fn write_to_precharge(&self) -> u64
pub fn write_to_precharge(&self) -> u64
WRITE → PRECHARGE, same bank: WL + BL/2 + tWR.
Sourcepub fn write_to_read(&self) -> u64
pub fn write_to_read(&self) -> u64
WRITE → READ, any bank: WL + BL/2 + tWTR.
Sourcepub fn read_to_write(&self) -> u64
pub fn read_to_write(&self) -> u64
READ → WRITE, any bank: BL/2 + 2, one idle clock between the read data and the write data.
Sourcepub fn cas_to_cas(&self) -> u64
pub fn cas_to_cas(&self) -> u64
Column command → column command in one direction: max(tCCD, BL/2), so no burst is cut short.
Sourcepub fn dram_timings(&self) -> DramTimings
pub fn dram_timings(&self) -> DramTimings
This clocked part as the DRAM table ddr2_ctrl and the planner read. The table counts write recovery from
the end of a burst issued with its command, so DDR2’s write latency rides in twr; it has one turnaround for
both directions, so tturn takes the longer, WRITE→READ. WRITE→PRECHARGE and WRITE→READ are then exact,
READ→WRITE is never shorter, and READ→PRECHARGE is the burst, exact while tRTP is two clocks: the table has
no term for a longer one.
Trait Implementations§
Source§impl Clone for Ddr2Timing
impl Clone for Ddr2Timing
Source§fn clone(&self) -> Ddr2Timing
fn clone(&self) -> Ddr2Timing
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read moreSource§impl Debug for Ddr2Timing
impl Debug for Ddr2Timing
Source§impl PartialEq for Ddr2Timing
impl PartialEq for Ddr2Timing
impl Copy for Ddr2Timing
impl Eq for Ddr2Timing
impl StructuralPartialEq for Ddr2Timing
Auto Trait Implementations§
impl Freeze for Ddr2Timing
impl RefUnwindSafe for Ddr2Timing
impl Send for Ddr2Timing
impl Sync for Ddr2Timing
impl Unpin for Ddr2Timing
impl UnsafeUnpin for Ddr2Timing
impl UnwindSafe for Ddr2Timing
Blanket Implementations§
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T: ?Sized,
impl<T> BorrowMut<T> for Twhere
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impl<T> CloneToUninit for Twhere
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further downcast into Rc<ConcreteType> where ConcreteType implements Trait.§fn as_any(&self) -> &(dyn Any + 'static)
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generate &Any’s vtable from &Trait’s.§fn as_any_mut(&mut self) -> &mut (dyn Any + 'static)
fn as_any_mut(&mut self) -> &mut (dyn Any + 'static)
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§fn equivalent(&self, key: &K) -> bool
fn equivalent(&self, key: &K) -> bool
key and return true if they are equal.