Function emit_ddr2_dfi_controller_verilog 

pub fn emit_ddr2_dfi_controller_verilog(t: &Ddr2Timing) -> String

Emit ddr2_dfi_ctrl for the clocked part t: every rule of t baked in, a DFI_CTRL_QUEUE-deep queue.

The part must be the one the 1:2 rate and the port assume: x16, eight banks, 1 Kb columns, burst length 4 (one burst a 64-bit word, a system clock of data), column commands two DRAM clocks apart at most, and eight refresh intervals and the queue’s drain inside tRAS max: a row opened just after a refresh stays open, at the longest, until the eighth refresh owed forces the queue to drain and every bank to precharge.