Module ddr2_dfi 

ddr2_dfi — ddr2_dfi_ctrl, the LOGOS DDR2 controller at the DFI 1:2 rate: a 64-bit native request port (a word a command, write data on its own stream, read data back in request order) and two DFI phases a system clock, the interface LiteDRAM’s controller presents to its PHY, so either drives the same PHY.

One BL4 burst of the x16 part is a 64-bit word and two DRAM clocks, one system clock: a column command every system clock is the bus’s whole bandwidth. The controller keeps one in-order queue of requests and three pointers into it: the tail takes requests, prep opens the row of the next request (bank lookahead: a row opens while earlier requests in other banks are still being served), and the head issues column commands, in request order, so read data comes back in request order and no reorder buffer is needed. A row stays open only while a prepared request still needs it or the next request to prepare reads it; otherwise its last column command closes it (auto-precharge), so a request that finds the controller idle pays ACT and the column command, not a precharge first. A row is open only while a prepared request needs it, or for the clock in which the next request to prepare takes it as a hit, so no request ever finds its bank open on another row: the only PRECHARGE the controller issues is the precharge-all before a refresh.

Column commands go on phase 0, row and refresh commands on phase 1. Every rule of the clocked part is a down-counter in DRAM clocks from the current system clock’s phase 0, decremented by two a clock: a column command may issue when its counters are 0, a row command when they are at most 1. tRRD and tFAW are a window over the last system clocks’ ACTs. Refresh is postponed while requests wait — up to the eight JESD79-2 allows — and repaid when the queue is empty or the debt reaches eight: then no new row opens, the prepared requests drain, every bank precharges and the REFRESH issues. A row is therefore never open longer than eight refresh intervals and the drain, inside tRAS max. Read data is delivered without back-pressure, as LiteDRAM’s crossbar delivers it.

Constants

DFI_CTRL_QUEUE

The requests ddr2_dfi_ctrl holds: the window its bank lookahead sees.

Functions

emit_ddr2_dfi_controller_verilog

Emit ddr2_dfi_ctrl for the clocked part t: every rule of t baked in, a DFI_CTRL_QUEUE-deep queue.