Module coproc_core 

coproc_core — the coprocessors, ISSUED as CPU instructions.

The crdt_merge / bigint_alu / bigint_mul blocks are real synthesized silicon, but on their own they are standalone datapaths. This module wires them into a genuine (if minimal) core: a program counter, a combinational instruction ROM, an 8×256-bit register file, and a decode → issue → retire pipeline. Each cycle it fetches rom[pc], decodes {op,rd,rs,rt}, ROUTES R[rs]/R[rt] into the addressed coprocessor, and RETIRES the result to R[rd] — exactly a CPU issuing a coprocessor instruction. Proven == the software oracle under iverilog, tied to the shipped BigInt/GCounter at the model level, and synthesized.

This is a DEMONSTRATOR core (five ops); the full 113-op LOGOS soft-core with these coprocessors on its issue port is the in-progress integration (SILICON_CAPABILITY_MAP).

ISA: op ∈ {0=HALT, 1=BADD, 2=BSUB, 3=BMUL, 4=CMERGE}; rd/rs/rt are 3-bit reg indices.

Constants

COPROC_A

Initial register-file operands (R0, R1); the rest reset to zero. Chosen with A > B (so the subtract has no underflow) and full-width carry/borrow activity.

COPROC_B

COPROC_PROGRAM

The demo program: issue each coprocessor op once, retire to a distinct register, then halt.

Functions

emit_coproc_core_testbench

Self-checking testbench: run the core to halt, read back R2..R5, compare to the oracle from coproc_exp.hex (the Rust model’s final register file). Prints PASS/FAIL.

emit_coproc_core_verilog

Emit the issuing core: PC + combinational ROM + 8×256-bit register file + decode/issue/retire, instantiating the real bigint_alu / bigint_mul / crdt_merge blocks as functional units.

run_core

A cycle-faithful Rust MODEL of the core: fetch → decode → issue → retire, over the same coprocessor semantics the RTL instantiates. Returns the final 8×256-bit register file. The iverilog testbench proves the RTL reproduces exactly this.

Type Aliases

Instr

One decoded instruction: (op, rd, rs, rt).