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emit_coproc_core_verilog

logicaffeine_compile::codegen_sva::coproc_core

Function emit_coproc_core_verilog 

Source 
pub fn emit_coproc_core_verilog(
    a: &[u64; 4],
    b: &[u64; 4],
    program: &[Instr],
) -> String
Expand description

Emit the issuing core: PC + combinational ROM + 8×256-bit register file + decode/issue/retire, instantiating the real bigint_alu / bigint_mul / crdt_merge blocks as functional units.