pub const WPE_PROJECT: CaravelProject;Expand description
The whole-program engine (wpe_caravel): its UART and its PSRAM on user GPIOs, clocked
on user_clock2 at the clock its UART bit period was derived from, faster than the chip signs its core clock
for. Its ports are held to the harness’s minimum input delays
(flow_config::vehicle_macro_sdc), so its hold margin is OpenLane’s placement default, 0.1 ns: the 0.7 ns the
command player carries buffered 35,656 of the engine’s paths.