Expand description
SVA/PSL Code Generation for Hardware Verification
Generates SystemVerilog Assertions (SVA), Property Specification Language (PSL), and Rust runtime monitors from temporal property specifications.
Modules§
- bitblast
- Bit-blasting:
BoundedExprdatapath (bitvector) operations → booleanProofExpr. - cdc
- Clock Domain Crossing (CDC) Formal Verification
- ci
- CI/CD Integration — SARIF Output for GitHub Security Tab
- controller_
gen - Designer → certified controller: turn a synthesized
PhasePlaninto a Verilog phase-FSM and let the existing RTL pipeline (parse_transition_system→prove_invariant) certify it. - coverage
- Specification Coverage Metrics
- fol_
to_ sva - FOL → SVA Formal Synthesis
- fol_
to_ verify - FOL → Bounded Verification IR Translation
- hw_
pipeline - Hardware Verification Pipeline
- power
- Power-Aware Formal Verification
- protocols
- Pre-Verified Protocol Templates
- rtl
- RTL / transition-system bounded model checking — including multi-bit (bitvector) registers.
- rtl_
extract - Verilog Declaration Parser
- rtl_kg
- RTL KG + Spec-RTL Linking
- signal_
design - Conflict-free traffic-signal PHASE DESIGNER (certified SAT synthesis).
- sufficiency
- Property Sufficiency Analysis
- sva_
model - SVA Semantic Model
- sva_
to_ proof - Bounded SVA/FOL obligation →
ProofExpr(the certified-prover seam). - sva_
to_ verify - SVA → Bounded Verification IR Translation
- sva_
vacuity - SVA Nonvacuous Evaluation Tracking (IEEE 16.14.8)
- synthesis_
refine - CEGAR Refinement for SVA Synthesis
- synthesize
- Sprint 5C: Top-Level Synthesis API
- traffic_
flow - Traffic FLOW / capacity analysis as model checking.
- verified_
compiler - Verified SVA Compiler via Futamura Projections
- verify_
to_ kernel - Spec Encoding: BoundedExpr → Kernel Term
- z3_
synth - Sprint 4A: Z3 Synthesis Constraint Builder
Structs§
- SvaProperty
- A single SVA property ready for emission.
Enums§
- SvaAssertion
Kind - Assertion type — determines the SVA wrapper.
Functions§
- emit_
psl_ property - Emit a single PSL property.
- emit_
rust_ monitor - Emit a Rust runtime monitor scaffold for a property.
- emit_
sva_ module - Emit multiple SVA properties as a complete module.
- emit_
sva_ property - Emit a single SVA property with its assertion wrapper.
- sanitize_
property_ name - Sanitize a human-readable property name into a valid SVA identifier. “Data Integrity” → “p_data_integrity”