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bit_serial_mul

logicaffeine_compile::codegen_dram::dataflow

Function bit_serial_mul 

Source 
pub fn bit_serial_mul(
    df: &mut DramDataflow,
    a: &[usize],
    b: &[usize],
    out_width: usize,
    zero: usize,
) -> Vec<usize>
Expand description

Bit-serial unsigned MULTIPLY (shift-add): for each bit i of b, add a (masked by plane b[i]) shifted up by i into an out_width-plane accumulator. Composed from AND + bit_serial_add — integer multiply from the boolean basis. Result is a·b mod 2^out_width per lane; zero is a zero row (accumulator seed + carry-in + high-plane filler).