Module eval 

Tier-1 behavioral evaluation of an analog netlist.

eval_analog_dc is the analog analogue of the digital fabric’s eval_grid: the IDEAL reference semantics. The plane settles to a DC operating point per control tick; with no non-ideality and unit scale, that point is exactly the SSA dataflow evaluated in f64 — the same operations in the same order as the VM, so the ideal tier is compared with logos_approx_eq and is bit-exact in practice. Physics (scales, quantization, mismatch, noise) enters through later layers, each with its own budgeted comparison — never here.

Structs

ConverterGrid

THE converter model — the single definition of the block scale and both converter grids every physical tier shares (the behavioral evaluators, the instance evaluator, the streamed and integrated steppers — and the mixed-signal SoC’s fixed-point surrogate, which must mirror these semantics bit-for-bit).

Functions

eval_analog_dc

Ideal DC operating point: evaluate the SSA tiles in order and read the output tap.

eval_analog_quantized

DC operating point through the CONVERTER path: each input is driven by the DAC (rounded to its LSB at the block scale), the plane settles in the VOLT domain (the Mul tile divides by its programmed V_ref, returning products to the block scale), and the output is read through the ADC (rounded to its LSB) and descaled exactly (power-of-two shift).