Struct RiscvQemu 

pub struct RiscvQemu;

RISC-V through its AOT tier (crate::compile::compile_to_riscv): the decode step as RISC-V assembly; a run links its generation program with its runtime (crate::codegen_riscv::runtime) by riscv64-linux-gnu-gcc once and runs it under qemu-riscv64.

Trait Implementations

impl Backend for RiscvQemu

fn name(&self) -> &'static str

The chip, as the command line names it.

fn bring_up( &self, spec: &ModelSpec, _checkpoint: &Path, ctx: usize, out: &Path, ) -> Result<Brought, Refused>

Lower spec’s program — the checkpoint at checkpoint — over caches of ctx positions, writing the artifacts under out.

fn run( &self, spec: &ModelSpec, checkpoint: &Path, ctx: usize, out: &Path, sequences: &[Sequence], ) -> Result<Generated, Refused>

Run the model on this chip, what Backend::bring_up wrote under out beside it: every one of sequences from an empty state, its prompt (token ids from 0) and then as many tokens as it is judged against, generated greedily through the one program — or refuse by name, a chip that is not on this machine, or whose run is not built yet, saying which.