#[repr(C, align(32))]pub struct Lanes8Word32(pub [u32; 8]);Expand description
Eight lanes of Word32 (one 256-bit SIMD register). Operations are lane-wise over the ℤ/2³² ring.
Tuple Fields§
§0: [u32; 8]Implementations§
Source§impl Lanes8Word32
impl Lanes8Word32
Sourcepub fn from_words(s: &[Word32]) -> Self
pub fn from_words(s: &[Word32]) -> Self
Pack the first eight Word32s of a slice into a lane vector (shorter slices zero-fill).
Sourcepub fn bitxor(self, o: Self) -> Self
pub fn bitxor(self, o: Self) -> Self
Lane-wise XOR (vpxor). #[inline(always)] + compile-time cfg(target_feature="avx2")
intrinsics so a hot Logos lane kernel (ChaCha/NTT) inlines register-resident under +avx2
(no per-op #[target_feature] call boundary — that pessimizes ~20× on Keccak-scale kernels).
Sourcepub fn bitand(self, o: Self) -> Self
pub fn bitand(self, o: Self) -> Self
Lane-wise AND (_mm256_and_si256) — the MD5 F/G-function bit mixing; LLVM lowers the loop to one
vpand. AND/OR/NOT have no cross-lane dependency, so the scalar form auto-vectorizes cleanly.
Sourcepub fn add(self, o: Self) -> Self
pub fn add(self, o: Self) -> Self
Lane-wise wrapping add in ℤ/2³² (vpaddd) — cfg-inline so it fuses into hot Logos lane kernels.
Sourcepub fn rotl(self, n: u32) -> Self
pub fn rotl(self, n: u32) -> Self
Lane-wise left rotation by n (ChaCha diffusion) — (x<<n)|(x>>(32−n)) via vpslld/vpsrld.
cfg-inline; n is taken mod 32 (n = 0 → the 32−n = 32 shift zeroes → identity).
Sourcepub fn sub(self, o: Self) -> Self
pub fn sub(self, o: Self) -> Self
Lane-wise wrapping subtract in ℤ/2³² (vpsubd) — the i32 NTT butterfly’s difference. cfg-inline.
Sourcepub fn montmul32(self, b: Self, q: Self, qinv: Self) -> Self
pub fn montmul32(self, b: Self, q: Self, qinv: Self) -> Self
The signed i32 Montgomery multiply — per lane montgomery_reduce(aᵢ·bᵢ) = (aᵢbᵢ − t·q)≫32,
t = (aᵢbᵢ mod 2³²)·qinv, the ML-DSA (Dilithium) NTT butterfly’s multiply (q = 8380417,
q,qinv broadcast). AVX2: vpmuldq the even and the (≫32) odd 32-bit lanes to eight i64
products, reduce each (the result lands in the high 32 bits), recombine with vpblendd.
Sourcepub fn ntt_bcast_lo(self, h: usize) -> Self
pub fn ntt_bcast_lo(self, h: usize) -> Self
Broadcast each 2h-block’s low h lanes into both halves — the within-vector NTT source-low
duplication for 8 i32 lanes, stride h ∈ {4,2,1}. h=4→vperm2i128(0x00) (128-bit halves);
h=2→vpshufd(0x44); h=1→vpshufd(0xA0). (The byte op is the i16 stride-2h shuffle.)
Sourcepub fn ntt_bcast_hi(self, h: usize) -> Self
pub fn ntt_bcast_hi(self, h: usize) -> Self
Broadcast each 2h-block’s high h lanes into both halves. h=4→vperm2i128(0x11);
h=2→vpshufd(0xEE); h=1→vpshufd(0xF5).
Trait Implementations§
Source§impl Add for Lanes8Word32
impl Add for Lanes8Word32
Source§impl BitAnd for Lanes8Word32
impl BitAnd for Lanes8Word32
Source§impl BitOr for Lanes8Word32
impl BitOr for Lanes8Word32
Source§impl BitXor for Lanes8Word32
impl BitXor for Lanes8Word32
Source§impl Clone for Lanes8Word32
impl Clone for Lanes8Word32
Source§fn clone(&self) -> Lanes8Word32
fn clone(&self) -> Lanes8Word32
1.0.0 (const: unstable) · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read moreSource§impl Debug for Lanes8Word32
impl Debug for Lanes8Word32
Source§impl Hash for Lanes8Word32
impl Hash for Lanes8Word32
Source§impl Not for Lanes8Word32
impl Not for Lanes8Word32
Source§impl PartialEq for Lanes8Word32
impl PartialEq for Lanes8Word32
Source§fn eq(&self, other: &Lanes8Word32) -> bool
fn eq(&self, other: &Lanes8Word32) -> bool
self and other values to be equal, and is used by ==.