Module word 

Fixed-width wrapping integers — the ring ℤ/2ᵏℤ.

Unlike crate::numeric::BigInt, whose arithmetic is exact and unbounded, a Word is total and wrapping: Word32::MAX.add(Word32::ONE) == Word32::ZERO. This is the natural home for the bit-twiddling primitives — ChaCha20 lives over Word32, Keccak over Word64 — where each operation is a single native instruction and the modular semantics are exact rather than an overflow into arbitrary precision. Rotation (rotl/rotr) is width-defined and lives only here.

Structs

Lanes4Word32

Four lanes of Word32 = one 128-bit register (__m128i) — the SHA-1 state/message carrier. Unlike the arithmetic lane types, its vocabulary is the four Intel SHA operations (sha1rnds4/sha1msg1/ sha1msg2/sha1nexte), so SHA-1 WRITTEN in Logos over these compiles to the sha1rnds4 hardware sequence (AOT) and runs the byte-identical software spec crate::sha_ops on the interpreter. Lane i is bits [32i+31 : 32i] — index 0 low, index 3 high — matching _mm_loadu_si128.

Lanes4Word64

Four lanes of Word64 (one 256-bit SIMD register) — the Poly1305 accumulator lane vector. Carries [u64; 4]; ops have an AVX2 fast path proven byte-identical to the scalar lanes.

Lanes8Word32

Eight lanes of Word32 (one 256-bit SIMD register). Operations are lane-wise over the ℤ/2³² ring.

Lanes16Word8

Sixteen Word8 lanes = one 128-bit register (__m128i) — the BYTE-SHUFFLE carrier for SIMD text codecs (hex encode/decode). Its vocabulary is shuffle (pshufb, a 16-entry byte LUT), byte AND, per-byte shift, and the two byte interleaves — so a hex codec WRITTEN in Logos over it compiles to the pshufb sequence (AOT, when SSSE3 is statically enabled) and runs the byte-identical scalar spec on the interpreter. Lane i is byte i (index 0 low), matching _mm_loadu_si128.

Lanes16Word16

Sixteen lanes of Word16 (one 256-bit SIMD register) — the NTT coefficient lane vector. Carries [u16; 16]; the multiply-high is the SIGNED _mm256_mulhi_epi16 (the Montgomery butterfly’s mulhi). Ops have an AVX2 fast path proven byte-identical to the scalar lanes.

Word8

A 8-bit wrapping integer: the ring ℤ/2^8ℤ, where every operation is total and wraps modulo 2^8.

Word16

A 16-bit wrapping integer: the ring ℤ/2^16ℤ, where every operation is total and wraps modulo 2^16.

Word32

A 32-bit wrapping integer: the ring ℤ/2^32ℤ, where every operation is total and wraps modulo 2^32.

Word64

A 64-bit wrapping integer: the ring ℤ/2^64ℤ, where every operation is total and wraps modulo 2^64.

Enums

LanesVal

A SIMD lane vector of any supported lane config — the single runtime carrier the interpreter/VM match on, mirroring WordVal. Binary ops require the same config; a mismatch returns None.

WordVal

A fixed-width wrapping integer of either supported width — the single runtime carrier for Word32/Word64 across the interpreter, VM, and wire, so the rest of the system matches on one Word value rather than a variant per width. Binary ops require matching widths; a width mismatch is a type error the caller reports (the ops return None).