logicaffeine_compile/spatial/decode_engine/mod.rs
1//! The LOGOS decode engine: a spatial dataflow on one card that holds its sequences' token-rows on chip and
2//! streams the weights through them once a pass.
3//!
4//! [`numerics`] is the engine's arithmetic, bit for bit: what every unit computes, so the hardware is held to it
5//! exactly and it is held to the model's own arithmetic within a measured bar. [`model`] runs a checkpoint in it.
6//! [`lane`] is the block-scale lane over the integer sums the array actually delivers; [`vector`] is the vector
7//! unit's instruction set and the micro-programs it runs; [`program`] is a checkpoint's step as the commands the
8//! units run, the list [`model`] interprets; [`machine`] runs it as the jobs the sequencer issues over the card's
9//! memory, every byte where it lives; [`twin`] prices a program command by command on the engine's units; [`rtl`]
10//! prints the units; [`ofs`] writes the D5005's accelerator build tree around them. [`image`] lays a checkpoint's
11//! weights over the card's memory channels in the order a pass reads them; [`physical`] places the rest of a machine's
12//! memory over the channels and names the streams of each sequence's state; [`ddr`] prices a pass's streams on those
13//! channels.
14
15pub mod capability;
16pub mod ddr;
17pub mod image;
18pub mod lane;
19pub mod lower_graph;
20pub mod machine;
21pub mod model;
22pub mod numerics;
23pub mod ofs;
24pub mod physical;
25pub mod program;
26pub mod rtl;
27pub mod shim;
28pub mod twin;
29pub mod vector;