Enum Expected 

pub enum Expected {
    Proves,
    DerivationNotCertified,
    CompilesToFol(&'static [&'static str]),
    OutputContains(&'static [&'static str]),
    NativeOnlyCompiles,
    KernelAllStatementsOk,
    KernelAdmitsAt(&'static str),
    SvaSynthesizes,
    SignalPlanSynthesizes,
    RtlProven,
    RefutesWithCounterexample,
    RegisterAllocFits,
    SpillsRequired,
    UnsatCertified,
}

The documented intended outcome an example is locked to. The test harness dispatches on this to the same pipeline the Studio uses for that mode.

Variants

Proves

Logic theorem: compile_theorem_for_ui(src).verified is true.

DerivationNotCertified

Logic theorem that intentionally yields a derivation the kernel does NOT certify — the string-door-honesty demonstration (the Barber paradox): the backward chainer finds a derivation, but the system honestly reports it is not a certified proof (derivation.is_some() && !verified).

CompilesToFol(&'static [&'static str])

Logic sentences: compile_for_ui(src) yields FOL (no error) whose BOTH the primary and the Simple views contain every content needle — so a silently-dropped modifier (e.g. an adverb lost when the Simple view flattens the event) fails the lock instead of passing unnoticed.

OutputContains(&'static [&'static str])

Code: runs in the baseline interpreter with no error, printing each needle.

NativeOnlyCompiles

Code that cannot run in the browser interpreter (real OS networking): it must still generate Rust cleanly.

KernelAllStatementsOk

Math: every statement executes without error in a fresh kernel Repl.

KernelAdmitsAt(&'static str)

Math intentionally open: statements execute until a documented admitted goal (the marker string names the open point, e.g. a termination wall).

SvaSynthesizes

Hardware English→SVA: synthesizes AND certifies equivalent to the spec.

SignalPlanSynthesizes

Hardware signal-design: yields a phase plan with at least one phase.

RtlProven

Verilog proven safe by k-induction (BMC fallback finds no counterexample).

RefutesWithCounterexample

Verilog unsafe by design: the prover MUST find a counterexample.

RegisterAllocFits

Register allocation that fits the register budget (certified valid).

SpillsRequired

Register allocation that provably must spill (certified spill).

UnsatCertified

Pigeonhole instance with a certified UNSAT (Hall) witness.

Trait Implementations

impl Clone for Expected

fn clone(&self) -> Expected

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Expected

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.