pub const RTL_EXAMPLES: &[(&str, &str)];Expand description
RTL examples: (filename, Verilog). Synthesizable Verilog the Studio parses into a
transition system and bounded-model-checks / k-induction-proves in the browser (no Z3).
Verified by the hardware_examples integration test. Opened in Hardware mode (they live
under /examples/hardware); load_hardware_spec routes module … endmodule content to
the RTL BMC path.