Module word_rt 

Runtime support for the Word8/Word16/Word32/Word64 ring types in COMPILED LOGOS.

Generated Rust constructs words with word32(x), rotates with rotl(x, n), and shows them. Arithmetic and bit operators (+, ^, &, …) already live as trait impls on the Word newtypes in [logicaffeine_base] — each delegating to the wrapping primitive — so the emitted a + b is ring-correct with no per-site wrapping_*. This module supplies the remaining glue the codegen names: the word* constructors, the width-generic rotl/rotr, and the Showable impls so Show renders a word as its decimal value (matching the tree-walker and VM byte-for-byte).

Structs

Lanes4Word32

Four lanes of Word32 = one 128-bit register (__m128i) — the SHA-1 state/message carrier. Unlike the arithmetic lane types, its vocabulary is the four Intel SHA operations (sha1rnds4/sha1msg1/ sha1msg2/sha1nexte), so SHA-1 WRITTEN in Logos over these compiles to the sha1rnds4 hardware sequence (AOT) and runs the byte-identical software spec [crate::sha_ops] on the interpreter. Lane i is bits [32i+31 : 32i] — index 0 low, index 3 high — matching _mm_loadu_si128.

Lanes4Word64

Four lanes of Word64 (one 256-bit SIMD register) — the Poly1305 accumulator lane vector. Carries [u64; 4]; ops have an AVX2 fast path proven byte-identical to the scalar lanes.

Lanes8Word32

Eight lanes of Word32 (one 256-bit SIMD register). Operations are lane-wise over the ℤ/2³² ring.

Lanes16Word8

Sixteen Word8 lanes = one 128-bit register (__m128i) — the BYTE-SHUFFLE carrier for SIMD text codecs (hex encode/decode). Its vocabulary is shuffle (pshufb, a 16-entry byte LUT), byte AND, per-byte shift, and the two byte interleaves — so a hex codec WRITTEN in Logos over it compiles to the pshufb sequence (AOT, when SSSE3 is statically enabled) and runs the byte-identical scalar spec on the interpreter. Lane i is byte i (index 0 low), matching _mm_loadu_si128.

Lanes16Word16

Sixteen lanes of Word16 (one 256-bit SIMD register) — the NTT coefficient lane vector. Carries [u16; 16]; the multiply-high is the SIGNED _mm256_mulhi_epi16 (the Montgomery butterfly’s mulhi). Ops have an AVX2 fast path proven byte-identical to the scalar lanes.

Word8

A 8-bit wrapping integer: the ring ℤ/2^8ℤ, where every operation is total and wraps modulo 2^8.

Word16

A 16-bit wrapping integer: the ring ℤ/2^16ℤ, where every operation is total and wraps modulo 2^16.

Word32

A 32-bit wrapping integer: the ring ℤ/2^32ℤ, where every operation is total and wraps modulo 2^32.

Word64

A 64-bit wrapping integer: the ring ℤ/2^64ℤ, where every operation is total and wraps modulo 2^64.

Traits

WordRotate

Width-defined bit rotation, available on every word width so rotl(x, n) is one name.

Functions

and_not4

andNot4(a, b) — Keccak χ’s (¬a) ∧ b in one lane op (vpandn). The compiled form of the builtin.

byte_add16

Per-byte wrapping add — compiled byteAdd16(a, b) (the ASCII→nibble decode).

hsum_lanes4

The horizontal sum of a Lanes4Word64’s lanes as an Int — the compiled form of hsumLanes4(v).

int_of_word16

The unsigned value of a Word16 as an Int (0..2¹⁶−1) — the compiled form of intOfWord16(w), the ML-KEM NTT’s Word16-coefficient → Int boundary.

int_of_word32

The unsigned value of a Word32 as an Int — the compiled form of intOfWord32(w), used to serialize a keystream word into bytes (Int mod/div) for the XOR against a Seq of Int payload.

int_of_word64

The value of a Word64 as an Int — intOfWord64(w). For values ≥ 2⁶³ this is a negative i64 (two’s-complement bits); used on byte-masked lanes (< 256) in Keccak’s squeeze.

interleave_hi16

High-eight byte interleave (_mm_unpackhi_epi8) — compiled interleaveHi16(a, b).

interleave_lo16

Low-eight byte interleave (_mm_unpacklo_epi8) — compiled interleaveLo16(a, b).

lanes4_of

Pack four Word32s straight into a SHA-1 lane register — compiled lanes4Of(a, b, c, d). The alloc-free constructor (no Seq, no heap): the Logos SHA-1 packs a lane this way every round.

lanes4_word32

Pack the first 4 Word32s of a Seq into a SHA-1 lane register — compiled lanes4Word32(s).

lanes4_word64

Pack the first 4 Ints of a Seq into a Lanes4Word64 — the compiled form of lanes4Word64(s).

lanes8_word32

Pack the first 8 Word32s of a Seq into a lane vector — the compiled form of lanes8Word32(s).

lanes16_word8

Pack the first 16 bytes of a Seq of Int into a byte-shuffle register — compiled lanes16Word8(s).

lanes16_word16

Pack the first 16 Ints of a Seq into a Lanes16Word16 — the compiled form of lanes16Word16(s).

maddubs16

Multiply-add adjacent byte pairs (pmaddubsw) — compiled maddubs16(a, w) (nibble-pair → byte).

montmul32

The signed i32 Montgomery multiply (vpmuldq) — the compiled form of montmul32(a, b, q, qinv), the ML-DSA NTT butterfly multiply.

mul32x32to64

Lane-wise widening low-32 multiply (vpmuludq) — the compiled form of mul32x32to64(a, b).

mulhi16

Lane-wise SIGNED high-16 multiply (vpmulhw) — the compiled form of mulhi16(a, b).

packus16

Pack two 8×i16 vectors to 16×u8 with unsigned saturation (packuswb) — compiled packus16(a, b).

rotl

Left rotation — the compiled form of rotl(x, n). The amount is taken as i64 (the type of a LOGOS Int) and reduced to the rotation width.

rotr

Right rotation — the compiled form of rotr(x, n).

seq_of_lanes4

Unpack a Lanes4Word64 into a Seq of 4 Int lanes — the compiled form of seqOfLanes4(v).

seq_of_lanes8

Unpack a lane vector into a Seq of 8 Word32 — the compiled form of seqOfLanes8(v).

seq_of_lanes4w32

The 4 lanes back as a Seq of Word32 — compiled seqOfLanes4W32(v).

seq_of_lanes16

Unpack a Lanes16Word16 into a Seq of 16 Int lanes (u16 bits) — seqOfLanes16(v).

seq_of_lanes16w8

The 16 bytes back as a Seq of Int — compiled seqOfLanes16W8(v).

sha1msg1

sha1msg1(a, b) — message-schedule step 1. Lowers to sha1msg1.

sha1msg2

sha1msg2(a, b) — message-schedule step 2. Lowers to sha1msg2.

sha1nexte

sha1nexte(a, b) — fold the next round E. Lowers to sha1nexte.

sha1rnds4

sha1rnds4(abcd, msg, func) — four SHA-1 rounds. Lowers to the sha1rnds4 instruction.

shr_bytes16

Per-byte logical shift right — compiled shrBytes16(v, n).

shuffle16

Byte shuffle (pshufb) — compiled shuffle16(table, idx).

splat4_word64

splat4Word64(x) — broadcast one Word64 into all four Keccak lanes (the ι round-constant XOR, and the all-ones vector for χ’s complement). The compiled form of the Logos builtin.

splat8_word32

Broadcast one Word32 into all 8 lanes — the compiled form of splat8Word32(x) (a crypto kernel loads a shared constant/key word into every block’s lane this way).

splat16_word8

Broadcast one byte into all 16 lanes — compiled splat16Word8(x).

splat16_word16

Broadcast a Word16/Int into all 16 lanes — the compiled form of splat16Word16(x).

word8

Construct a word from the low bits of an integer — the compiled form of word32(x) etc.

word16

word32

word64

word32_shr

word32Shr(w, n) — logical shift-right of a Word32 by n bits (SHA-256’s σ0/σ1 message schedule, where the shift is NOT a rotate — the vacated high bits are zero).

word64_and

word64And(a, b) — bitwise AND of two Word64s (Keccak χ’s ¬b ∧ c, and byte masking).

word64_shl

word64Shl(w, n) — logical shift-left of a Word64 by n bits (Keccak lane byte-packing).

word64_shr

word64Shr(w, n) — logical shift-right of a Word64 by n bits (Keccak squeeze byte-extract).

word_and

Bitwise AND/OR/NOT — the compiled form of word_and/word_or/word_not. Distinct from the and/or keywords (logical short-circuit) so word crypto written in LOGOS (the MD5/SHA-1 round functions) is bit-exact on every tier. Word8/16/32/64 impl these operators, so they lower to a single machine and/or/not; a lane vector lowers to the AVX2 vector form.

word_not

word_or