Module regalloc 

Contiguous register-allocated region codegen — the EXODIA 3.1 “closer” foundation (WS-G).

Where crate::jit::compile_straightline_coded lowers ONE stencil PIECE per MicroOp (each piece re-establishing operands from the frame, doing its op, storing the result, and tail-calling the next), this backend emits the WHOLE supported region as ONE contiguous x86-64 function. A global register assignment keeps the hottest slots resident in physical registers across every op, so a reg-resident operand is read with a register move (or used directly) rather than a frame round-trip — eliminating the per-piece ABI/operand overhead that holds the tiered cluster at 3-6× V8.

Soundness contract (the differential gate is sacred)

The emitted function is BIT-IDENTICAL to crate::jit::reference_eval and thus to the tree-walker:

• i64 wrapping arithmetic (x86 add/sub/imul wrap natively);
• the kernel’s exact shift spec (count truncates to the low 6 bits via cl);
• Div/Mod side-EXIT on a zero divisor BEFORE any effect (a ChainOutcome::Deopt through the shared status cell, replayed on bytecode where the kernel raises the precise error), and reproduce MIN / -1 = MIN / MIN % -1 = 0 without the #DE overflow trap.

On exit (every Return) ALL reg-resident slots are flushed back to the frame, so the frame the caller observes is consistent with the tree-walker’s full frame state — the region tier can resume / deopt from frame slots.

Assignment model

A slot is either RESIDENT (lives in one fixed physical register for the whole function) or SPILLED (lives in its frame slot). Slots are ranked by reference count; the top ones that fit get the allocatable callee/caller saved GPRs. This is a global per-slot assignment (no per-point churn), so it is trivially correct across loops and back-edges: a slot is always in the same place. rax/rdx/rcx are reserved scratch (arithmetic, division, shift count); r15 holds the frame base pointer.

Functions

compile_function_regalloc

Compile a recursive FUNCTION’s micro-op stream into ONE contiguous register-allocated x86-64 function — including its DIRECT self-calls (CallSelf/CallSelfCopy) — callable through the crate::buffer::JitChain ABI. Returns None (caller falls back to the per-piece stencil tier) on any unsupported op (a cross-function Call, list/map ops, byte arrays, …) or a missing terminator.

compile_function_regalloc_precise

Compile a LIST-PARAMETER (mode-B) recursive FUNCTION — one that mutates a SHARED pinned array in place and may self-call — into ONE contiguous register-allocated x86-64 function with PRECISE deopt. Returns None (caller falls back to the per-piece stencil tier) on any unsupported op.

compile_region_regalloc

Compile a region of micro-ops into ONE contiguous register-allocated x86-64 function, callable through the crate::buffer::JitChain ABI. Returns None (caller falls back to the stencil tier) when the region contains an unsupported op or has no terminating Return/Jump.

compile_region_regalloc_precise

Compile a PRECISE REGION — the in-place-array-mutation shape that ALSO does a reallocating ArrPush (the fannkuch permutation rebuild, the graph_bfs BFS frontier) — into ONE contiguous register-allocated x86-64 region with PRECISE deopt. Returns None (caller falls back to the per-piece precise stencil tier) on any unsupported op or a missing terminator.

regalloc_enabled

Whether the contiguous register-allocating backend is selected. Default ON: it is bit-identical to the stencil tier (proven by the full corpus differential with the flag on) and 4-6x faster on the regions it supports, falling back to the per-piece tier on any unsupported op. LOGOS_REGALLOC=0 is the kill-switch. Read once.

simd_enabled

LOGOS_SIMD=1 opts a recognized PURE ELEMENT-WISE MAP region (Oracle-proven in-bounds, unit-stride, no loop-carried scalar — see crate::vectorize::recognize_elementwise_map) into a 2-wide packed-double loop. DEFAULT OFF: the bit-identical differential gate must certify it before promotion, and no current benchmark exercises a float map. Read once.