Module isa 

R6 — the Tier-5 Silicon ISA emitter. The register-VM opcode set becomes the native ISA; each stencil family maps to a functional unit. This lowers a CompiledProgram to LOGOS Silicon ISA assembly — the SAME opcodes the interpreter/VM/JIT/AOT run, now as the chip’s instruction set.

Every emitted instruction carries its RevClass — the adiabatic datapath contract: • Bijection instructions run backward with ZERO garbage (the charge-recovery core); • Journaled instructions push a minimal Bennett delta; • Effectful instructions hit the effect log / a named irreversibility barrier; • Control instructions reverse on the recorded trace.

Because the classifier reversibility is TOTAL over the ISA (no NonReversible, enforced by reverse_op_lock), the emitter can never lower an unclassified — hence non-reversible-by-omission — instruction. The isa_aot_lock test pins that: every op emits, and every emission is classified.

Structs

AdiabaticSchedule

The adiabatic cell budget of a program — the count of each CellClass its Silicon datapath needs. The charge_recovery fraction is the adiabatic (zero-erasure) share; a program with no ancilla or effect cells is FULLY ADIABATIC — its Landauer floor is 0, since no cell can erase a bit.

Enums

CellClass

The physical cell a Silicon-ISA instruction maps to — the structured (machine-checkable) form of the rev_tag annotation, one per RevClass. This is the datapath’s adiabatic contract: ChargeRecovery cells recycle their charge (zero erased bits); AncillaWrite cells write a Bennett history bit (the only genuine erased-bit source); the rest carry no erased data.

SiliconStatus

Where each ISA op lives in silicon — the FULL-SURFACE map. Every op has a home, so the WHOLE language is silicon-implementable: the realized reversible datapath, the ALU/value datapath (the build frontier), the instruction sequencer, the load/store + structured-memory unit, or an off-core coprocessor (runtime services). This is an EXHAUSTIVE match with no wildcard — a new Op cannot compile until it declares its silicon home, so the chip can never silently fail to cover a language feature. CoreDatapath is a monotone floor that RISES as datapath ops are realized in RTL and proven ≡ VM by our certified SAT (the silicon_op_support_ratchet lock).

Functions

adiabatic_schedule

Compute the AdiabaticSchedule — the per-CellClass cell budget — for a program.

cell_class

The cell an op maps to — derived from the TOTAL reversibility classifier, so it is exhaustive by construction (the census NonReversible is provably empty, mapped conservatively to an ancilla cell). Keep in lockstep with rev_tag.

coprocessor_realized

The concurrency/coprocessor ops realized as on-core services in soft_core.v: the FIFO-channel NoC (a fixed ring buffer on the heap), proven by the ≡VM differential (buffered send/receive is byte-identical to the VM’s deterministic pipe) + iverilog, decoded at their binisa wire opcodes.

emit_isa

Emit prog as LOGOS Silicon ISA assembly text, every instruction annotated with its reversibility class. Totality is guaranteed by the classifier: an unclassified op cannot compile the crate.

load_store_realized

The load-store ops realized in the soft-core’s heap unit (soft_core.v’s dmem/hp + the run_soft_core model): sequence construction, push, indexed read, and length. Proven by the the_soft_core_runs_logos_programs_identically_to_the_vm differential (heap ≡ VM RuntimeValue::List) and decoded at their binisa wire opcodes by the soft_core_decodes_the_wire_opcodes lock.

rev_tag

The reversibility-contract tag for one ISA instruction — the adiabatic annotation the Silicon backend reads to decide whether an instruction charge-recovers (Bijection) or needs a history cell.

silicon_realized

Whether an op is REALIZED in synthesizable silicon TODAY — it has emitted RTL AND its operation is proven correct by our own certified SAT (not merely classified). This is the ratchet’s PROGRESS metric; it grows as Datapath ops are turned into verified hardware. Two realized units: the reversible charge-recovery core (rev_alu_core.v; each op proven a bijection/injective) and the general integer ALU (codegen_sva::rtl::emit_alu_datapath_verilog; arithmetic/bitwise/signed- comparison ops proven correct by the our-SAT identity battery the_general_alu_datapath_is_proven _correct_by_our_sat). RAISE SILICON_REALIZED_FLOOR as ops graduate — never lower it.

silicon_status

The silicon home of an op — EXHAUSTIVE (no wildcard), so the full ISA is provably mapped to hardware and a new op must declare its home. Keep the CoreDatapath arm in lockstep with the realized rev_alu_core.v datapath (binisa opcodes 0..4).

soft_core_executes

The ops the fetch-decode-execute soft-core (benchmarks/silicon/soft_core.v) itself decodes and executes — the movement + control-flow + output ops (as opposed to the value-transform ALU ops proven by our-SAT identities). Realized by the CPU running real bytecode (iverilog-proven) and by the soft_core_decodes_the_wire_opcodes lock tying its decode to binisa::opcode.