Expand description
What the spatial chips run whole (CUDA persistent, Tensix, the RDU, the fabric): their answer to the shared optimizer.
A spatial chip lowers each op of the one IR to sections of the closed compute algebra — matrix tiles, row maps, reductions, recurrent and attention sections — places them on its sites and schedules the whole step as one program. It links one fused class whole: a region of pointwise ops, its members’ sections joined into one, each value it makes handed from the member that makes it to the one that reads it and never stored. Every other fused op runs as its parts, each its own sections, and the spatial passes join sections after lowering. A class turns native here when the spatial link builds it as one section. Placements are refused: a section reads and writes each tensor through its own access map, never a part of another op’s.
Structs§
- Spatial
Shim - A spatial chip, by the target its sections are lowered for.