Struct RduChipFacts 

pub struct RduChipFacts {

    pub chip: RduChip,
    pub part: &'static str,
    pub peak_bf16_tflops: Fact<u32>,
    pub peak_fp8_tflops: Option<Fact<u32>>,
    pub silicon_peak_bf16_pflops: Fact<f64>,
    pub sram_mib: Fact<usize>,
    pub hbm_gib: Fact<usize>,
    pub ddr_gib_max: Fact<usize>,
    pub pmu_kib: Option<Fact<usize>>,
    pub hbm_bandwidth_gbps: Fact<f64>,
    pub ddr_bandwidth_gbps: Fact<f64>,
    pub p2p_tb_s: Fact<f64>,
    pub node_nm: Fact<u32>,
    pub dies: Fact<u32>,
    pub chips_per_node: Fact<usize>,
    pub scale_up: Option<Fact<ScaleUp>>,
    pub pcu_count: Fact<usize>,
    pub pmu_count: Fact<usize>,
    pub witnessed: &'static [Precision],
    pub witness_pending: &'static [Precision],
    pub index_datatype: Fact<Precision>,
    pub unit_model: RduUnitModel,
    pub cites: &'static [&'static str],
    pub others: &'static [OtherFigure],
}

The facts of one RDU generation.

Fields

chip: RduChip

part: &'static str

peak_bf16_tflops: Fact<u32>

Peak dense BF16 throughput per RDU, TFLOPS.

peak_fp8_tflops: Option<Fact<u32>>

Peak dense FP8 throughput per RDU, TFLOPS — None where the vendor publishes no FP8 figure.

silicon_peak_bf16_pflops: Fact<f64>

The bf16 roofline the SiliconSpec publishes, in PFLOPS: per RDU on the SN50; on the SN40L the 16-socket node figure the descriptor has carried since its lock (16 × 640 TFLOPS).

sram_mib: Fact<usize>

The capacities, each in the binary unit the vendor counts in (BINARY): SRAM in MiB, HBM and the largest DDR in GiB.

hbm_gib: Fact<usize>

ddr_gib_max: Fact<usize>

pmu_kib: Option<Fact<usize>>

One PMU’s scratchpad, KiB — None where the vendor publishes no count of them.

hbm_bandwidth_gbps: Fact<f64>

Peak HBM bandwidth per RDU, GB/s.

ddr_bandwidth_gbps: Fact<f64>

Peak DDR bandwidth per RDU, GB/s.

p2p_tb_s: Fact<f64>

Aggregate chip-to-chip bandwidth per RDU, TB/s.

node_nm: Fact<u32>

dies: Fact<u32>

chips_per_node: Fact<usize>

RDUs per node — the tensor-parallel width a fit report shards across.

scale_up: Option<Fact<ScaleUp>>

The scale-up fabric, where the vendor tabulates it.

pcu_count: Fact<usize>

pmu_count: Fact<usize>

witnessed: &'static [Precision]

Precisions our fabric places AND witnesses — the only ones the descriptors advertise.

witness_pending: &'static [Precision]

Chip-supported precisions no witness has shipped for — never advertised, named in the envelope.

index_datatype: Fact<Precision>

The integer type the PCU computes indices and addresses in: the widest integer compute datatype the part has. Every index a lowering carries onto the chip — a gathered row, an arg-max, a block start — rides it, and the integer accumulator of the matrix path is this wide; nothing wider exists on the part.

unit_model: RduUnitModel

cites: &'static [&'static str]

The bibliography keys (benchmarks/samba_papers.tsv) of the sources the facts cite: a published fact’s citation opens with its source’s key and the figure as that source states it.

others: &'static [OtherFigure]

The figures sources state that the facts do not carry.

Implementations

impl RduChipFacts

pub fn of(chip: RduChip) -> RduChipFacts

pub fn sn40l() -> RduChipFacts

The SN40L: 1040 PCUs and 1040 PMUs of 512 KB at TSMC 5 nm, 638 TFLOPS bf16 a socket, 16 sockets a node, a three-tier memory of 520 MiB on-chip SRAM, 64 GiB of HBM at 1.6 TB/s and up to 1.5 TiB of DDR at over 100 GB/s. The PCU’s compute datatypes are BF16 / FP32 / INT32 / INT8: INT8 + BF16 are witnessed on the matrix path, FP32 is chip-supported and witness-pending, and INT32 is the index datatype.

pub fn sn50() -> RduChipFacts

The SN50: TSMC 5 nm, two max-reticle logic dies, 1600 TFLOPS BF16 / 3200 TFLOPS FP8, 432 MB on-chip SRAM, 64 GB HBM2E, DDR5 up to 512 GB (the datasheet: up to 2 TB), 8 chips per node and 16 per SambaRack, ten 800G ports a chip (seven make the node’s full mesh, two reach the inter-node fabric) carrying 2 TB/s, 400G RoCEv2 scale-out. The PCU/PMU counts are NOT public (“a sea of PCUs and PMUs”) — inherited from the SN40L and labeled modeled, and so are the HBM and DDR bandwidths. FP8 and FP32 are chip-supported and witness-pending.

pub fn with_pcu_stages(self, stages: Fact<usize>) -> RduChipFacts

pub fn with_pmu_banks(self, banks: Fact<usize>) -> RduChipFacts

pub fn with_credit(self, credit: Fact<CreditLatency>) -> RduChipFacts

pub fn with_pcu_count(self, count: Fact<usize>) -> RduChipFacts

pub fn with_pmu_count(self, count: Fact<usize>) -> RduChipFacts

pub fn with_hbm_gib(self, hbm: Fact<usize>) -> RduChipFacts

pub fn hbm_gbps(&self) -> Fact<f64>

The co-packaged HBM’s bandwidth, GB/s.

pub fn clock_ghz(&self) -> Fact<f64>

The clock the unit model counts cycles in, GHz. Not published for either part: Plasticine’s.

pub fn roofs(&self) -> Roofs

The roofs: the modeled HBM bandwidth over the clock, and the published matrix peaks per RDU. The vendor publishes no INT8 or on-chip rate, so those resources carry no roof.

pub fn sram_bytes(&self) -> usize

pub fn local_mem_bytes_per_pcu(&self) -> usize

The on-chip SRAM spread over the PCUs — one site’s local-memory budget.

pub fn mesh(&self) -> MeshShape

The modeled mesh: the PCU count laid out into mesh_columns columns; a count the aspect cannot tile is laid out as one row.

pub fn target_modeled(&self) -> &'static [&'static str]

The modeled set of the derived SpatialTarget — a function of which counts are modeled: a modeled PCU count makes the mesh, the per-site memory and the silicon’s compute-tile figure modeled; a modeled PMU count makes the mem-tile figure modeled. The mesh aspect, the accumulator depth and the tile geometry are modeled on every RDU.

pub fn modeled_fields(&self) -> Vec<String>

Every modeled fact, by dotted path, sorted — read by reflection over the serialized facts so the ledger cannot drift from the data.

pub fn fabric_target(&self) -> FabricTarget

The scalar-fabric envelope of one PCU datapath: what place_with_target places onto, gated by the witnessed precisions and the three memory tiers; the silicon block carries the published tile counts (or the modeled ones, so labeled on the mesh descriptor).

pub fn spatial_target(&self) -> SpatialTarget

The spatial mesh: one site per PCU, the SRAM spread over them, a crossbar switch fabric, token / valid-ready / barrier handshakes, and the embedded scalar datapath.

Trait Implementations

impl Clone for RduChipFacts

fn clone(&self) -> RduChipFacts

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for RduChipFacts

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for RduChipFacts

fn eq(&self, other: &RduChipFacts) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Serialize for RduChipFacts

fn serialize<__S>(&self, __serializer: __S) -> Result<__S::Ok, __S::Error>

where __S: Serializer,

Serialize this value into the given Serde serializer.

impl StructuralPartialEq for RduChipFacts