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HP_PORT_BYTES
logicaffeine_
compile
0.11.0
In logicaffeine_
compile::
spatial::
fpga_
decode
logicaffeine_compile
::
spatial
::
fpga_decode
Constant
HP_
PORT_
BYTES
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Source
pub const HP_PORT_BYTES:
f64
= 16.0;
Expand description
Bytes one 128-bit AXI HP port carries in a PL clock cycle.